ANALYSIS, VERIFICATION AND FPGA IMPLEMENTATION OF VEDIC MULTIPLIER WITH BIST CAPABILITY A thesis report submitted in the partial fulfillment of the requirement for the award of the degree of Master of Technology in VLSI Design & CAD Submitted by Vinay Kumar Roll No.: 60761026 Under the Guidance Of Mr. Arun Kumar Chatterjee Lecturer, ECED
Department of Electronics and Communication Engineering THAPAR UNIVERSITY (Formerly Known as Thapar Institute of Engineering and Technology) PATIALA-147004, INDIA June – 2009
I hereby declare that the work which is being presented in the thesis entitled, “Analysis, Verification and FPGA Implementation of Vedic Multiplier with BIST Capability” in partial fulfillment of the requirement for the award of degree of M.Tech (VLSI Design & CAD) at electronics and Communication Department of Thapar University, Patiala, is an authentic record of my own work carried out under the supervision of Mr. Arun Kumar Chatterjee, Lecturer, ECED. The matter presented in this thesis has not been submitted in any other University/Institute for the award of my degree.
Vinay Kumar Roll.No. 60761026
It is certified that the above statement made by the student is correct to the best of my knowledge and belief.
Mr. Arun Kumar Chatterjee Lecturer ECED, Thapar University Patiala -147004
Dr. A. K. Chatterjee Professor & Head Electronics and Communication Engg. Department Thapar University, Patiala - 147004
Dr. R. K. Sharma Dean Academic Affairs Thapar University Patiala – 147004
To discover, analyze and to present something new is to venture on an untrodden path towards and unexplored destination is an arduous adventure unless one gets a true torchbearer to show the way. I would have never succeeded in completing my task without the cooperation, encouragement and help provided to me by various people. Words are often too less to reveals one‟s deep regards. I take this opportunity to express my profound sense of gratitude and respect to all those who helped me through the duration of this thesis. I acknowledge with gratitude and humility my indebtedness to Mr. Arun Kumar Chatterjee, Lecturer, ECED, Thapar University, Patiala, under whose guidance I had the privilege to complete this thesis. I wish to express my deep gratitude towards her for providing individual guidance and support throughout the thesis work. I convey my sincere thanks to Dr.A.K.Chatterjee, Professor & Head of Electronics & Communication Department, Thapar University, Patiala for his encouragement and cooperation. I express my heartfelt gratitude towards Mrs. Alpana Agarwal, Assistant Professor & PG coordinator, ECED, Thapar University, Patiala, for their valuable guidance, encouragement, inspiration and the enthusiasm with which she solved my difficulties in VLSI Design & CAD Lab. I would also like to thank all staff members and my co-students who were always there at the need of the hour and provided with all the help and facilities, which I required for the completion of my thesis. My greatest thanks are to all who wished me success especially my parents. Above all I render my gratitude to the Almighty who bestowed self-confidence, ability and strength in me to complete this work for not letting me down at the time of crisis and showing me the silver lining in the dark clouds.
Vinay Kumar ii
This thesis work is devoted for the design of a high speed Vedic multiplier, its implementation on reconfigurable hardware and Built in Self Testing (BIST) of the implemented multiplier. Interfacing of FPGA with a PS2 KEYBOARD has also been done. For arithmetic multiplication various Vedic multiplication techniques like Urdhva tiryakbhyam, Nikhilam and Anurupye has been thoroughly discussed. It has been found that Urdhva tiryakbhyam Sutra is most efficient Sutra (Algorithm), giving minimum delay for multiplication of all types of numbers, either small...
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