Multipliers, Algorithms, and Hardware Designs

Mahzad Azarmehr Supervisor: Dr. M. Ahmadi

Spring 2008

Multipliers, Algorithms and Hardware Designs

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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR

Outline

• • Survey Objectives Basic Multiplication Schemes

•Shift/Add Multiplication Algorithm •Basic H d B i Hardware M lti li Multiplier

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High-Radix Multipliers

•Multiplication of Signed Numbers •Radix-4 Multiplication •Modified Booth’s Recoding

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Tree and Array Multipliers

•Using Carry-save Adders •Full Tree Multipliers •High-Radix Multipliers •Alternative Reduction Trees •Tree Multipliers for signed numbers •Divide and Conquer Design •Array Multipliers y p •Additive Multiply Modules •Pipelined Tree and Array Multipliers •Bit-Serial Multipliers •Modular Multipliers •Squaring

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Variation in Multipliers

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Conclusion

Multipliers, Algorithms and Hardware Designs

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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR

Survey Objectives S Obj ti

• Multiplication is a heavily used arithmetic operation that figures prominently in signal processing and scientific applications Multiplication is hardware intensive, and the main criteria of interest are higher speed, lower cost, and less VLSI area The main concern in classic multiplication, often realized by K cycles of shifting and adding, is to speed up the underlying multi-operand add t o of partial products addition o pa t a p oducts In this survey, a variety of multiplication algorithms and hardware designs are di d i discussed d 3

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Multipliers, Algorithms and Hardware Designs

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR

Shift/Add Multiplication Algorithm

• With the following notation: a Multiplicand ak-1ak-2…a1a0 x Multiplier p Product xk-1xk-2…x1x0 p2k-1p2k-2…p1p0

Each row corresponds to the product of the multiplicand and a single bit of multiplier. Each term is either 0 or a

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Binary multiplication reduces to adding a set of numbers, each of which is 0, or shifted version of the multiplicand a

Multipliers, Algorithms and Hardware Designs

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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR

Shift/Add Multiplication Algorithm

• Sequential multiplication can be done by a cumulative partial product (initialized to 0) and successively adding to it the properly shifted terms xja p(j+1) = (p(j) + xja2k) 2-l • Instead of shifting successive numbers to the left for alignment, cumulative partial product is shifted by one bit to the right The product will have a total shift of k bits to the right, right so we pre-multiply a by 2k to offset this effect 5

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Multipliers, Algorithms and Hardware Designs

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR

Basic Hardware Multiplier

• • x and p are stored in shift registers The next bit of x is used to select 0 or a for addition Shifting can be performed by connecting the (i)th sum output to the (k+i-1)th bit of the partial product register and the adder’s carry out to bit 2k-1 bt x and lower half of p can share the same register i 6

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Multipliers, Algorithms and Hardware Designs

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR

Multiplication of Signed Numbers

• In signed-magnitude numbers, the product’s sign should be computed separately by XORing the operand signs In 2’s-complement representation: • • Negative multiplicand, the same routine with sign-extended values Negative multiplier, the term xk-1a should be subtracted rather than added in the last cycle

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In practice, the required subtraction is performed by adding the 2’scomplement of the multiplicand or adding its 1’s-complement and inserting a carry-in of 1 into the adder carry in 7

Multipliers, Algorithms and Hardware Designs

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