Radix4 Booth Multiplier

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR

Multipliers, Algorithms, and Hardware Designs

Mahzad Azarmehr Supervisor: Dr. M. Ahmadi

Spring 2008

Multipliers, Algorithms and Hardware Designs

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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR

Outline
• • Survey Objectives Basic Multiplication Schemes
•Shift/Add Multiplication Algorithm •Basic H d B i Hardware M lti li Multiplier

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High-Radix Multipliers

•Multiplication of Signed Numbers •Radix-4 Multiplication •Modified Booth’s Recoding

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Tree and Array Multipliers

•Using Carry-save Adders •Full Tree Multipliers •High-Radix Multipliers •Alternative Reduction Trees •Tree Multipliers for signed numbers •Divide and Conquer Design •Array Multipliers y p •Additive Multiply Modules •Pipelined Tree and Array Multipliers •Bit-Serial Multipliers •Modular Multipliers •Squaring

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Variation in Multipliers

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Conclusion

Multipliers, Algorithms and Hardware Designs

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Survey Objectives S Obj ti
• Multiplication is a heavily used arithmetic operation that figures prominently in signal processing and scientific applications Multiplication is hardware intensive, and the main criteria of interest are higher speed, lower cost, and less VLSI area The main concern in classic multiplication, often realized by K cycles of shifting and adding, is to speed up the underlying multi-operand add t o of partial products addition o pa t a p oducts In this survey, a variety of multiplication algorithms and hardware designs are di d i discussed d
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Multipliers, Algorithms and Hardware Designs

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR

Shift/Add Multiplication Algorithm
• With the following notation: a Multiplicand ak-1ak-2…a1a0 x Multiplier p Product xk-1xk-2…x1x0 p2k-1p2k-2…p1p0

Each row corresponds to the product of the multiplicand and a single bit of multiplier. Each term is either 0 or a

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Binary multiplication reduces to adding a set of numbers, each of which is 0, or shifted version of the multiplicand a

Multipliers, Algorithms and Hardware Designs

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Shift/Add Multiplication Algorithm
• Sequential multiplication can be done by a cumulative partial product (initialized to 0) and successively adding to it the properly shifted terms xja p(j+1) = (p(j) + xja2k) 2-l • Instead of shifting successive numbers to the left for alignment, cumulative partial product is shifted by one bit to the right The product will have a total shift of k bits to the right, right so we pre-multiply a by 2k to offset this effect
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Multipliers, Algorithms and Hardware Designs

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR

Basic Hardware Multiplier
• • x and p are stored in shift registers The next bit of x is used to select 0 or a for addition Shifting can be performed by connecting the (i)th sum output to the (k+i-1)th bit of the partial product register and the adder’s carry out to bit 2k-1 bt x and lower half of p can share the same register i
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Multipliers, Algorithms and Hardware Designs

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR

Multiplication of Signed Numbers
• In signed-magnitude numbers, the product’s sign should be computed separately by XORing the operand signs In 2’s-complement representation: • • Negative multiplicand, the same routine with sign-extended values Negative multiplier, the term xk-1a should be subtracted rather than added in the last cycle

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In practice, the required subtraction is performed by adding the 2’scomplement of the multiplicand or adding its 1’s-complement and inserting a carry-in of 1 into the adder carry in
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Multipliers, Algorithms and Hardware Designs

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Multiplication of Signed Numbers
• Examples of 2’s-complement multiplications:

Multipliers, Algorithms and Hardware Designs

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Multiplication using Booth’s Recoding Booth s
• • The more 1s there are in x, the slower the multiplication In Booth’s recoding, every sequence of 1s is replaced with a sequence of 0s a -1 in the 0s, least significant end, and addition of 1 in the next higher position: 2j+2j-1+ +2i+1+2i = 2j+1-2i +…+2 2 xi 0 0 1 1 xi-1 0 1 0 1 yi 0 1 -1 0 explanation No string of 1s in sight End of string of 1s Beginning of string of 1s Continuation of string of 1s

Multipliers, Algorithms and Hardware Designs

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High-Radix High Radix Multipliers
• These multiplication schemes handle more than one bit of the multiplier in each cycle

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A higher representation radix leads to fewer digits. Thus, a digit-at-atime multiplication algorithm requires fewer cycles as we move to higher radices, which means fewer partial products The reduction in the number of cycles, along with the use of cycles recoding and carry-save adders, leads to significant gains in speed over basic multipliers

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Multipliers, Algorithms and Hardware Designs

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Radix-4 Radix 4 Multipliers
• Based on two least significant end bits of multiplier, a pre-computed multiple of a is added Alternately, rather than adding 3a, add –a and send a carry of 1 into the next radix-4 digit of the multiplier radix 4

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Multipliers, Algorithms and Hardware Designs

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Modified Booth’s Recoding Booth s
• If radix 4 multiplication is performed with the recoded multiplier, only radix-4 the multiples of ±a and ±2a will be required, all of which are easily obtained by shifting and/or complementation xi+1 0 0 0 0 1 1 1 1

xi
0 0 1 1 0 0 1 1

xi-1
0 1 0 1 0 1 0 1

yi+1
0 0 1 1 -1 -1 0 0

yi
0 1 -1 0 0 1 -1 0

explanation No string of 1s in sight End of a string of 1s Isolated 1 in x End of a string of 1s Beginning of a string of 1s End one string, begin new string Beginning of a string of 1s Continuation of string of 1s C ti ti f ti f1

Multipliers, Algorithms and Hardware Designs

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Radix-4 Radix 4 Multipliers
• Booth s Booth’s recoding is fully paralleled and carry-free

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non0: 1 bit to distinguish 0 from nonzero digits neg: 1 bit to show the sign of nonzero digit two: 1 bit to show the magnitude of nonzero digit 13

Multipliers, Algorithms and Hardware Designs

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Using Carry Save Adders Carry-Save
• Carry save Carry-save adders (CSA) can be used to reduce the number of addition cycles as well as to make each cycle faster A row of binary FA is used as a mechanism to reduce three numbers to two numbers, rather than finding a single “sum”

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Multipliers, Algorithms and Hardware Designs

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Wallace and Dadda trees
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Wallace’s strategy is to combine the partial product bits at the earliest opportunity, opportunity which leads to the fastest possible design With Dadda’s method, combining takes place as late as possible and usually

leads to simpler CSA tree and a wider CPA

Multipliers, Algorithms and Hardware Designs

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Using Carry Save Adders Carry-Save
• A carry save adder tree can reduce n carry-save binary numbers to two numbers having the same sum in O(log n) levels As an example, this CSA tree, reduces seven k-bit operands to two (k+2)-bit operands Not necessarily all the operands have the th same alignment li t

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Multipliers, Algorithms and Hardware Designs

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Using Carry Save Adders Carry-Save
• Radix 4 Radix-4 multiplication without Booth’s recoding can be implemented by using a CSA to handle the 3a multiple The drawback is that the add time is slightly increased since the increased, CSA overhead is paid in every cycle, regardless of whether 3a is actually needed

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Multipliers, Algorithms and Hardware Designs

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Using Carry Save Adders Carry-Save
• CSA can be put to better use for reducing the addition time by keeping the cumulative partial product in stored-carry form As the three values that form the next cumulative partial product are added, one bit of the final product is obtained and shifted into the lower half of the register This eliminates register. the need for carry propagation in all but the final addition

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Multipliers, Algorithms and Hardware Designs

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Using Carry Save Adders Carry-Save
• The previous CSA-based design CSA based can be combined with radix-4 Booth’s recoding to reduce the number of cycles by 50%, while also making each cycle considerably faster

Multipliers, Algorithms and Hardware Designs

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Using Carry Save Adders Carry-Save
• In the Booth recoding logic and multiple selection circuit, the sign of each multiple must be incorporated in the multiple itself, rather than as a signal that controls addition/subtraction This configuration can be used for high-radix and parallel multipliers

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Multipliers, Algorithms and Hardware Designs

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Using Carry Save Adders Carry-Save
• This is another way to accommodate the required 3a multiple Four numbers (the sum and carry components of the cumulative partial products xia and 2xi+1a) products, need to be combined, thus necessitating a two-level CSA tree

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Multipliers, Algorithms and Hardware Designs

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High-Radix High Radix Multipliers
• Now, it is an easy step to visualize a higher-radix multiplier: • In radix-2b multiplication with Booth’s recoding, we have to reduce b/2 multiples to 2 using a (b/2+2)-input (b/2+2) input CSA tree whose other two inputs are taken by the carry-save partial products. Without Booth’s recoding a Booth s (b+2)-input CSA tree would be needed

Multipliers, Algorithms and Hardware Designs

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Tree and Array Multipliers
• Tree, or fully parallel multipliers constitute limiting cases of high-radix high radix multipliers (radix-2k ) With a high-performance CSA tree followed by a fast adder, logarithmic time multiplication becomes possible The resulting multipliers are expensive, but justifiable, for applications in which multiplication speed is critical One-sided CSA trees lead to much slower, but highly regular, structures known as array multipliers that offer higher pipelined throughput than tree multipliers and significantly lower chip area

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Multipliers, Algorithms and Hardware Designs

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Full-Tree Full Tree Multipliers
• In full tree multipliers, all the k full-tree multiples of multiplicand are produced at once and a k-input CSA tree is used All the multiples are combined in one pass; the tree does not require feedback links, making pipelining quite feasible

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Multipliers, Algorithms and Hardware Designs

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Reduction Tree R d ti T
• A logarithmic depth reduction tree based on CSA has an irregular CSA, structure that makes its design and layout quite difficult Additionally, connections and signal paths of varying lengths lead to logic hazards and signal skew that have implications for both performance and power consumption Compared to generic CSA, the only modification required is relative shifting of the operands to be added

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Multipliers, Algorithms and Hardware Designs

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Reduction Tree

Multipliers, Algorithms and Hardware Designs

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Alternative Reduction Trees
• A slice of (n;2) counter when suitably counter, replicated, can perform the function of the reduction tree Using counters assures us that all outputs are produced after the same number of full-adder d l b f f ll dd delays The structure can be replicated to form an n-input reduction tree of desired width. Such balanced-delay trees are q quite suitable for VLSI implementation of p parallel multipliers
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Multipliers, Algorithms and Hardware Designs

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR

Alternative Reduction Trees
• Another alternative is using a module that reduces four numbers to two as the basic building block Then partial products reduction trees can be structured as binary trees that possess a recursive structure, making them more regular and easier to layout

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Multipliers, Algorithms and Hardware Designs

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Tree multipliers for signed numbers
• In multiplying 2’s-complement 2 s-complement numbers directly, partial products are signed numbers To avoid having to deal with negatively weighted bits, an efficient method offered by Baugh ff ff and Wooley: x -x0 = ¯ 0 -1

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Multipliers, Algorithms and Hardware Designs

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Array Multipliers
• A tree multiplier, with a one-sided multiplier reduction tree and a ripple-carry final adder is called an array multiplier an array multiplier is very regular in its structure and uses only short wires that go from one FA to adjacent FA It has a very simple and efficient y y layout in VLSI and can be easily and efficiently pipelined
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Multipliers, Algorithms and Hardware Designs

RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR

Array Multipliers
• Sum outputs are connected diagonally, while the carry outputs are linked vertically, except in the last row, where they are chained from right to left Baugh and Wooley method can be easily applied to array multiplier for 2’s-complement multiplication

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Multipliers, Algorithms and Hardware Designs

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Pipelined Tree and Array Multipliers
• Xi inputs are delayed through the insertion of latches in their paths and the product emerges with a latency of 2k-1 cycles 2k 1 FA blocks used are assumed to have output latches f both sum for and carry The final ripple-carry adder has been pipelined as well

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Multipliers, Algorithms and Hardware Designs

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Divide and Conquer Design
• A 2b×2b multiplier can be synthesized using b×b multiplier Although there are four partial products, only three values need to be added 2b×2b multiplication has been reduced to 4 b×b multiplications and a three-operand addition

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Multipliers, Algorithms and Hardware Designs

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Divide and Conquer Design
• For 2b×2b multiplication one can use b-bit adders exclusively to accumulate the partial products

Multipliers, Algorithms and Hardware Designs

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Additive Multiply Modules (AMMs)
• In certain computations, multiplications are commonly followed by additions. In such cases, implementing a multiply-add unit to compute p=ax+y might be cost effective. Furthermore, AMMs can be used as F th AMM b d building blocks for multipliers In a b×c AMM: (2b-1)(2c-1)+(2b-1)+(2c-1)=2b+c-1 • The cost of a 4×2 AMM is less than the p combined costs of a 4×2 multiplier and a 4bit adder
Inputs marked with an asterisk carry 0s Multipliers, Algorithms and Hardware Designs 35

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Bit-Serial Bit Serial Multipliers
• Bit-serial arithmetic is attractive in view of its smaller pin count count, reduced wire length, and lower floor space requirements in VLSI The compactness of the design may allow it to run a bit-serial multiplier at a high enough clock rate to make it competitive with much more complex designs with regard to speed

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Multipliers, Algorithms and Hardware Designs

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RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS - UNIVERSITY OF WINDSOR

Bit-Serial Bit Serial Multipliers
• For a latency-free multiplier, the relationship between the output and inputs are written in the form of a recurrence: a(0)=a0 , a(1)=(a1a0)2 , … , a(i)=2iai+a(i-1) p(i)=2-(i+1) a(i) x(i) , 2p(i)=p(i-1)+aix(i-1)+xia(i-1)+2iaixi

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A (5;3) counter can be used as an adder, if p(i1) is stored in double-carry-save form

Multipliers, Algorithms and Hardware Designs

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Modular Multipliers
• A modular multiplier is one that produces the product of two (unsigned) integers modulo some fixed constant m. The two special cases of m=2b and m=2b-1 are simpler to deal with If the partial products are accumulated through carry save addition carry-save addition,

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for m=2b, the output carry in position b-1 is ignored for m=2b-1, the carry out of position b-1 is combined with bits in column 0

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Multipliers, Algorithms and Hardware Designs

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Modular Multipliers
• Similar techniques can be used to handle modular multiplication in the general case As an example, a modulo-13 multiplier can be designed by using identities: 16 3 16=3 mod 13 32=6 mod 13 64=12 mod 13 3→2 1 2+1 6 → 4+2 12→ 8+4

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Multipliers, Algorithms and Hardware Designs

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Squaring
• Any standard or modular multiplier can be used for computing p=x2 if both inputs are connected to x A special-purpose k-bit squarer, if built in hardware, will be f significantly lower in cost and delay than a k×k multiplier • • x i xi → x i xixj + xjxi → 2xixj

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Multipliers, Algorithms and Hardware Designs

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Conclusion
• The classic shift/add multiplication schemes and their implementation have been examined There are two ways to speed up the underlying multi-operand addition; reducing th number of operands l d t hi h di multipliers, and d i i d i the b f d leads to high-radix lti li d devising hardware multi-operand adders that minimize the latency and/or maximize the throughput leads to tree and array multipliers Cost, VLSI area, and pin limitations favor bit-serial designs, while the desire g g py to use available building blocks leads to designs based on Additive Multiply Modules (AMMs) Finally, the Fi ll th special case of squaring was of interest, as it l d t i l f i fi t t leads to considerable simplification
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Multipliers, Algorithms and Hardware Designs

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Questions and Comments

Multipliers, Algorithms and Hardware Designs

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