Ee476 Course Notes
Acknowledgments
These course notes were originally developed by me for EE476 in Fall 1996 at Washington State University (WSU). The material in these notes has been derived from several sources. These include Dr. Venu Gopinathan's course notes from Columbia University, Dr. David Rich's analog IC design course notes, Prof. Terri Fiez's EE476 course notes, and Prof. Paul Gray's EE240 lecture notes. Their contributions to these notes are gratefully acknowledged. Also a significant amount of the material is based on the Gray and Meyer textbook. Prof. George La Rue at WSU made a monumental effort in cleaning up and formatting the original hand written notes in MS-WORD. I thank him for this effort and for providing me with the formatted notes. This …show more content…
SiO2
A unique property of Si is that the SiO2 oxide layer thickness can be controlled very uniformly Diffusion
5) Strip resist leaving patterned SiO2
Photolithography
Deposit a layer of material on surface Boron for P-type and Arsenic or Phosphorus for N-type
Page 17 EE 422/522
Page 18 EE 422/522
Raise temperature to ~ 1000o C to allow impurities to diffuse into substrate and replace Si atoms Highest impurity concentration at surface Ion Implantation Atoms are inserted at high energy into substrate Must be annealed at ~800o C to activate and reduce damage to substrate Most common method because Very uniform across wafer Peak of impurity profile can be below surface
Layout Example of PMOS Transistor
P-type Source and drains gate N-well contact Via
Metal 1 Metal 2
Deposition and Etching
Deposition Various materials need to be deposited on the wafers to fabricate circuits Chemical vapor deposition (CVD) is a common method to apply polysilicon, silicon nitride (Si3N4) and other dielectrics Metals are typically evaporated onto the wafers Etching Used to remove materials with high precision Wet etching plasma etching Reactive ion etching
Contacts N-well
Page 19 EE 422/522
Page 20 EE …show more content…
An increase in results in no further increase in xD but electrons
Page 21 EE 422/522
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can flow from the source/drain. This forms a channel between source and drain. The voltage on the gate required to produce inversion is called the threshold voltage, VT.
VT
F
VT 0
2
F
VSB
2
F
N KT ln( A ) where n is the intrinsic impurity concentration i q ni
VT ms 2
Qdep
F
Cox
ms
QSS Cox
of silicon.
is the work function difference between gate metal and Si.
Derivation of Non-saturation Equation
QSS is the surface charge at Si – SiO2 interface. Cox is the capacitance per unit area of the gate oxide.
L W v
VT
2
F
ms
QSS Cox
VT0
Qdep 0 Cox
Qdep
Qdep 0 Cox
C o r r e c t io n te rm
F
If QA is the charge per unit area, then the current
F
Qdep Qdep
Qdep 0 Cox Qdep 0 Cox
2qN A Cox
2qN A 2
VSB Cox
F
2qN A 2
I
Q t
Q AW
(vt ) t
Q AWv , where the v is the velocity.
Now consider the channel when VGS > VT and VDS = 0.
2qN A Cox
2
These course notes were originally developed by me for EE476 in Fall 1996 at Washington State University (WSU). The material in these notes has been derived from several sources. These include Dr. Venu Gopinathan's course notes from Columbia University, Dr. David Rich's analog IC design course notes, Prof. Terri Fiez's EE476 course notes, and Prof. Paul Gray's EE240 lecture notes. Their contributions to these notes are gratefully acknowledged. Also a significant amount of the material is based on the Gray and Meyer textbook. Prof. George La Rue at WSU made a monumental effort in cleaning up and formatting the original hand written notes in MS-WORD. I thank him for this effort and for providing me with the formatted notes. This …show more content…
SiO2
A unique property of Si is that the SiO2 oxide layer thickness can be controlled very uniformly Diffusion
5) Strip resist leaving patterned SiO2
Photolithography
Deposit a layer of material on surface Boron for P-type and Arsenic or Phosphorus for N-type
Page 17 EE 422/522
Page 18 EE 422/522
Raise temperature to ~ 1000o C to allow impurities to diffuse into substrate and replace Si atoms Highest impurity concentration at surface Ion Implantation Atoms are inserted at high energy into substrate Must be annealed at ~800o C to activate and reduce damage to substrate Most common method because Very uniform across wafer Peak of impurity profile can be below surface
Layout Example of PMOS Transistor
P-type Source and drains gate N-well contact Via
Metal 1 Metal 2
Deposition and Etching
Deposition Various materials need to be deposited on the wafers to fabricate circuits Chemical vapor deposition (CVD) is a common method to apply polysilicon, silicon nitride (Si3N4) and other dielectrics Metals are typically evaporated onto the wafers Etching Used to remove materials with high precision Wet etching plasma etching Reactive ion etching
Contacts N-well
Page 19 EE 422/522
Page 20 EE …show more content…
An increase in results in no further increase in xD but electrons
Page 21 EE 422/522
Page 22 EE 422/522
can flow from the source/drain. This forms a channel between source and drain. The voltage on the gate required to produce inversion is called the threshold voltage, VT.
VT
F
VT 0
2
F
VSB
2
F
N KT ln( A ) where n is the intrinsic impurity concentration i q ni
VT ms 2
Qdep
F
Cox
ms
QSS Cox
of silicon.
is the work function difference between gate metal and Si.
Derivation of Non-saturation Equation
QSS is the surface charge at Si – SiO2 interface. Cox is the capacitance per unit area of the gate oxide.
L W v
VT
2
F
ms
QSS Cox
VT0
Qdep 0 Cox
Qdep
Qdep 0 Cox
C o r r e c t io n te rm
F
If QA is the charge per unit area, then the current
F
Qdep Qdep
Qdep 0 Cox Qdep 0 Cox
2qN A Cox
2qN A 2
VSB Cox
F
2qN A 2
I
Q t
Q AW
(vt ) t
Q AWv , where the v is the velocity.
Now consider the channel when VGS > VT and VDS = 0.
2qN A Cox
2