Vlsi Implementation of Serial-Serial Multiplier Based on Asynchronous Counter Accumulation

Topics: Counter, Flip-flop, Logic gate Pages: 7 (1686 words) Published: December 28, 2012
International Conference on Computing and Control Engineering (ICCCE 2012), 12 & 13 April, 2012

VLSI Implementation of Serial-Serial Multiplier
based on Asynchronous Counter Accumulation
Y. Arun Benjamin Francis
Abstract—Multipliers are the fundamental and essential building blocks of VLSI systems. The design and implementation approaches of multipliers contribute substantially to the area, speed and power consumption of computation intensive VLSI system. The objective of the project is to design for applications with high data sampling rate. In the multiplier the partial product are effective ly formed by the dependency graph so that for an nxn multiplication the number of sampling cycles reduced from 2n to n. The full adder in the

conventional multiplier is replaced by asynchronous counters so that the critical path is limited to only one AND gate.
Keywords—Very large scale integration, asynchronous counter. I. INTRODUCTION


ERIAL multipliers are popular for their low area and
power, and are more suitable for bit -serial signal
processing applications with I/O constraints and on -chip
serial-link bus architectures. Often, the delay of multipliers dominates the critical path of these systems and due to issues concerning reliability and portability, power consumption is a critical criterion for applications that demand low-power as its primary metric. While low power and high speed multiplier

circuits are highly demanded, it is not always possible to
achieve both criteria simultaneously. Therefore, a good
multiplier design requires some tradeoff between speed and
power consumption

multiplier that is modular in structure and can operate on both signed and unsigned numbers. The 1-bit slice of a typical
serial-serial multiplier, called a bit-cell (BC), is excerpted from is shown . Such cells are interconnected to produce the output in a bit-serial manner for an serial-serial multiplier. The operands bits and are loaded serially in each cycle and added with the far carry, local carry, and the partial sum in the5:3 counter.

To reduce the number of computational cycles from 2n to n
in an nxn serial multiplier, several serial-parallel multipliers have been developed over the years. Most of them are based
on a carry save add shift (CSAS) structure. It shows the
unsigned and 2’s complement serial-parallel multiplier based on the CSAS structure. It can be observed that the critical path consists of an FA, a DFF, and an AND gate for the unsigned
This section proposes a new technique of generating the
individual row of partial products by considering two serial inputs, one starting from the LSB and the other from MSB.
Using this feeding sequence and the proposed counter -based
accumulation technique is presented, it takes only n cycles to complete the entire partial product generation and
accumulation process for an nxn multiplication. The
theoretical underpinning of this design is elaborated as

In a serial-serial multiplier both the operands are loaded in a bit-serial fashion, reducing the data input pads to two [2]. On the other hand, a serial-parallel multiplier loads one operand in a bit-serial fashion and the other is always available for

parallel operation [7]. Lyon [1] proposed a bit-serial input output multiplier in 1976 which features high throughput at
the expense of truncated output. A full precision bit -serial multiplier was introduced by Strader et al. for unsigned
numbers [3]. The rudimentary cell consists of a 5:3 counter
and some DFFs. Later, Gnanasekaran [5] extended the work in
[2] and developed the first bit-serial multiplier that directly handles the negative weight of the most significant bit (MSB) in 2’s complement representation. This method needs only
cells for an n-bit multiplication but it introduces an XOR gate in the critical path, which ends up with a more...
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