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Design Procedure for Two-Stage CMOS Opamp With Flexible Noise-Power Balancing Scheme Jirayuth Mahattanakul, Member, IEEE, and Jamorn Chutichatuporn Abstract—This paper presents a basic two-stage CMOS opamp design procedure that provides the circuit designer with a means to strike a balance between two important characteristics in electronic circuit design, namely noise performance and power consumption. It is shown in this paper that, unlike the previously reported design procedures, the proposed design step allows opamp designers to trade between noise performance and power consumption with greater flexibility. In order to verify the viability of the proposed design step, SPICE simulation results of the opamp designed by the proposed procedure, under a variety of temperature and process conditions, are given. Index Terms—CMOS analog integrated circuits, frequency compensation, operational amplifier, poles and zeroes. Fig. 1. Basic two-stage CMOS opamp.

I. INTRODUCTION MOS opamps are ubiquitous integral parts in various analog and mixed-signal circuits and systems. The two-stage CMOS opamp shown in Fig. 1 is widely used because of its simple structure and robustness. In designing an opamp, numerous electrical characteristics, e.g., gain-bandwidth, slew rate, common-mode range, output swing, offset, all have to be taken into consideration. Furthermore, since opamps are designed to be operated with negative-feedback connection, frequency compensation is necessary for closed-loop stability. Unfortunately, in order to achieve the required degree of stability, generally indicated by phase margin, other performance parameters are usually compromised. As a result, designing an opamp that meets all specifications needs a good compensation strategy and design methodology. The simplest frequency compensation technique employs the across Miller effect by connecting a compensation capacitor the high-gain stage. A design procedure for this type of opamp can be found in [1]. However, due to an unintentional feed-forward path through the Miller capacitor, a right-half-plane (RHP) zero is also created and the phase margin is degraded. Such a zero, however, can be removed if a proper nullifying resistor is inserted in series with the Miller capacitor [1]–[5]. A design procedure for the zero-nullification opamp can be found in [2]. is an imIt will be shown in Section III that the value of portant factor when determining noise and power, e.g., by decreasing , power consumption can be reduced but at the expense of noise performance. Unfortunately, one of the necesManuscript received February 13, 2003; revised June 22, 2004 and December 13, 2004. This paper was recommended by Associate Editor P. Wambacq. J. Mahattanakul is with the Mahanakorn University of Technology, Bangkok 10530, Thailand ( J. Chutichatuporn is with the RGY Hydraulic Company, Cholburi 20170, Thailand (e-mail: Digital Object Identifier 10.1109/TCSI.2005.851395


sary imposing conditions of the design procedure in [2] is being much larger than the parasitic capacitance associated with the input node of the high-gain stage. This condition thus reduces one important degree-of-freedom in analog circuit design, namely the tradeoff between noise and power consumption. In this work, it has been shown that by employing such a technique, the value of the compensation capacitor, , can be made much smaller than when employing other techniques. As provides such, the flexibility of choosing a wider range of the designer with a greater degree of freedom to optimize the opamp in terms of noise and power. II. BASIC OPAMP EQUATIONS For simplicity, both the mobility reduction due to the normal field and the velocity saturation effect associated with MOS devices will be neglected. The following MOSFET, strong-inversion, square-law equations: (1)...
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