MT-027: ADC Architectures VIII: Integrating ADCs
by Walt Kester and James Bryant
Rev. 0, 02-13-06
Soon after the discovery of the basic counting ADC architectures (see Tutorial MT-026) it was realized that much greater accuracy could be obtained using a combination of integrating and counting techniques. This led to the development of high accuracy dual-slope, triple-slope, and quad-slope ADCs. Although the proliferation of high resolution sigma-delta ADCs has made integrating architectures somewhat less popular, they are still used in a variety of precision applications such as digital voltmeters, etc.
Introduced in the 1950s, the "dual-slope" ADC architecture was truly a breakthrough in ADCs for high resolution applications such as digital voltmeters, etc. (see References 1-4). A simplified diagram is shown in Figure 1, and the integrator output waveforms are shown in Figure 2.
Figure 1: Dual Slope Integrating ADC
The input signal is applied to an integrator; at the same time a counter is started, counting clock pulses. After a pre-determined amount of time (T), a reference voltage having opposite polarity is applied to the integrator. At that instant, the accumulated charge on the integrating capacitor is proportional to the average value of the input over the interval T. The integral of the reference is an opposite-going ramp having a slope of VREF/RC. At the same time, the counter is again counting from zero. When the integrator output reaches zero, the count is stopped, and the analog circuitry is reset. Since the charge gained is proportional to VIN × T, and the equal amount of charge lost is proportional to VREF × tx, then the number of counts relative to the full scale count is proportional to tx/T, or VIN/VREF. If the output of the counter is a binary number, it will therefore be a binary representation of the input voltage.
Figure 2: Dual Slope ADC Integrator Output Waveforms
Dual-slope integration has...
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