Digital Electronics: EC64-VLSI Design Question Paper

IMMANUAL ARASAR COLLEGE OF ENGINEERING, NATTALAM
DEPARTMENT OF ELECTRONICS AND COMMUNICATION INTERNAL TEST- II YEAR:III

EC64-VLSI DESIGN Time:2hrs

PART-A 5*2=10

1.What are the test fixtures required to test a chip?
2.State the objective of functionality test.
3.Draw a pseudo NMOS inverter.
4.What are the advantage of using a PSEUDO N-MOS GATE instead of a full CMOS gate.
5.Write a note on CMOS transmission gate logic. PART-B

1.Describe the adhoc testing,BIST technique and scan based approaches to design for testability in detail.(16)
2.Explain the manufacturing test principles in detail.(10)
3.Describe the basic principle of operation of dynamic CMOS,domino and NP domino logic with neat diagrams.(10)
4.Write the basic principle of low power logic design.(4)
5.Explain the principle of SILICON DEBUG.(10)
6.Explain the detail about pseudo-nMOS gates with neat circuit diagram.(10)

IMMANUAL ARASAR COLLEGE OF ENGINEERING, NATTALAM
DEPARTMENT OF ELECTRONICS AND COMMUNICATION INTERNAL TEST- II YEAR:III

EC64-VLSI DESIGN Time:2hrs

PART-A 5*2=10

1.What are the test fixtures required to test a chip?
2.State the objective of functionality test.
3.Draw a pseudo NMOS inverter.
4.What are the advantage of using a PSEUDO N-MOS GATE instead of a full CMOS gate.
5.Write a note on CMOS transmission gate logic. PART-B

1.Describe the adhoc testing,BIST technique and scan based approaches to design for testability in detail.(16)
2.Explain the manufacturing test principles in detail.(10)
3.Describe the basic principle of operation of dynamic CMOS,domino and