Implementation of Low Power VLSI Circuit using

Pseudo NMOS Logic with Delay Elements

S.THANGAMALAR

M.E (VLSI DESIGN) P.G.SCHOLAR

DEPARTMENT OF E.C.E

SRI VENKATESWARA COLLEGE OF ENGINEERING AND TECHNOLOG

Email:rachelmalar@gmail.com

Abstract-The advent of dynamic CMOS logic, more precisely domino logic, made them widely used for the implementation of low power VLSI circuits. However, the main drawback of this logic is the non implementation of inverted logic. To implement the inverted logic, it is required to duplicate the logic circuit up to that part with inverted inputs. This obviously results the increase in area, delay as well as the power dissipation of the circuit. On the other hand, it is very simple to realize the circuit with both the inverted and non-inverted logic using pseudo NMOS implementation. In any transition either the pull up or pull down network is activated meaning the input capacitance of the inactive network loads the input. Moreover pmos transistors have poor mobility and must be sized larger to achieve comparable rising and falling delays further increasing input capacitance. In this paper, this problem is addressed with the realization of the circuit which requires the implementation of inverted logic using pseudo nmos logic. Pseudo NMOS and dynamic gates offer improved speed by removing the PMOS transistors from loading the input. To show the efficiency of the proposed model, a simple example like implementation of high fan-in NAND gate cascaded with AND gate is considered. With the comparison of all the three logics with a fixed fan-in of 7, 8 and 9 for both the gates, on an average 62.7% improvement is achieved in Power Delay Product (PDP), 10.4% improvement in area in terms of transistors using pseudo nmos logic implementation over static logic implementation and 65.64% improvement in PDP and 25.4% improvement in area over dynamic CMOSimplementation when designed in 180nm technology.

Keywords- Low Power VLSI; Static CMOS; Domino Logic;Pseudo NMOS; Power Delay Product I INTRODUCTION

For the implementation of low-power and high-speed VLSI circuits, dynamic CMOS in particular domino logic is the logic of choice. However, domino logic has many inherent limitations like charge leakage, charge sharing, clock skew etc. The main disadvantage in implementing domino logic is that it can implement only non-inverting logic. The requirement of implementation of inverted logic forces the designer to duplicate the entire circuit before that inverter with opposite polarities of inputs which increases the number of gates in the circuit which in turn increases the power dissipation and delay of the entire circuit. Hence the efficiency of domino logic is challenged if the circuit requires the implementation of more intermediate inverters. The implementation of static CMOS is efficient as it can implement both the inverted and noninverted logic. However static CMOS logic is slower than dynamic logic and suffers from large area and high short circuit power dissipation. On the other hand dynamic CMOS logic has less transistor count and zero short circuit power dissipation. Now considering the advantages of both logic styles, in this paper, novel circuit architecture, using pseudo nmos and dynamic CMOS logic has been proposed. Very few attempts have been made to implement a given circuit using pseudo nmos logic. Out of which an approach called two phase static-domino design used two out of phase clocks, master and slave flip flops. In the first domino evolution phase, domino logic and static CMOS logic gets evaluated but the output of static CMOS logic is fed to domino logic only in the second phase of evaluation. The presence of two clocks in this design results in inevitable problems like clock skew and clock routing overheads. The requirement of mid-cycle latches between two domino phases often degrades the performance of the circuit. In another approach , instead of static inverter in...