Implementation of Low Power Vlsi Circuit Using Pseudo Nmos Logic with Delay Elements
Implementation of Low Power VLSI Circuit using
Pseudo NMOS Logic with Delay Elements
S.THANGAMALAR
M.E (VLSI DESIGN) P.G.SCHOLAR
DEPARTMENT OF E.C.E
SRI VENKATESWARA COLLEGE OF ENGINEERING AND TECHNOLOG
Email:rachelmalar@gmail.com
Abstract-The advent of dynamic CMOS logic, more precisely domino logic, made them widely used for the implementation of low power VLSI circuits. However, the main drawback of this logic is the non implementation of inverted logic. To implement the inverted logic, it is required to duplicate the logic circuit up to that part with inverted inputs. This obviously results the increase in area, delay as well as the power dissipation of the circuit. On the other hand, it is very simple to realize the circuit with both the inverted and non-inverted logic using pseudo NMOS implementation. In any transition either the pull up or pull down network is activated meaning the input capacitance of the inactive network loads the input. Moreover pmos transistors have poor mobility and must be sized larger to achieve comparable rising and falling delays further increasing input capacitance. In this paper, this problem is addressed with the realization of the circuit which requires the implementation of inverted logic using pseudo nmos logic. Pseudo NMOS and dynamic gates offer improved speed by removing the PMOS transistors from loading the input. To show the efficiency of the proposed model, a simple example like implementation of high fan-in NAND gate cascaded with AND gate is considered. With the comparison of all the three logics with a fixed fan-in of 7, 8 and 9 for both the gates, on an average 62.7% improvement is achieved in Power Delay Product (PDP), 10.4% improvement in area in terms of transistors using pseudo nmos logic implementation over static logic implementation and 65.64% improvement in PDP and 25.4% improvement in area over dynamic CMOSimplementation when designed in 180nm technology.
Keywords- Low Power VLSI; Static CMOS; Domino
Pseudo NMOS Logic with Delay Elements
S.THANGAMALAR
M.E (VLSI DESIGN) P.G.SCHOLAR
DEPARTMENT OF E.C.E
SRI VENKATESWARA COLLEGE OF ENGINEERING AND TECHNOLOG
Email:rachelmalar@gmail.com
Abstract-The advent of dynamic CMOS logic, more precisely domino logic, made them widely used for the implementation of low power VLSI circuits. However, the main drawback of this logic is the non implementation of inverted logic. To implement the inverted logic, it is required to duplicate the logic circuit up to that part with inverted inputs. This obviously results the increase in area, delay as well as the power dissipation of the circuit. On the other hand, it is very simple to realize the circuit with both the inverted and non-inverted logic using pseudo NMOS implementation. In any transition either the pull up or pull down network is activated meaning the input capacitance of the inactive network loads the input. Moreover pmos transistors have poor mobility and must be sized larger to achieve comparable rising and falling delays further increasing input capacitance. In this paper, this problem is addressed with the realization of the circuit which requires the implementation of inverted logic using pseudo nmos logic. Pseudo NMOS and dynamic gates offer improved speed by removing the PMOS transistors from loading the input. To show the efficiency of the proposed model, a simple example like implementation of high fan-in NAND gate cascaded with AND gate is considered. With the comparison of all the three logics with a fixed fan-in of 7, 8 and 9 for both the gates, on an average 62.7% improvement is achieved in Power Delay Product (PDP), 10.4% improvement in area in terms of transistors using pseudo nmos logic implementation over static logic implementation and 65.64% improvement in PDP and 25.4% improvement in area over dynamic CMOSimplementation when designed in 180nm technology.
Keywords- Low Power VLSI; Static CMOS; Domino