lab1_32x32_registerfile
Fre-E CSE471 - Computer Organization and Design
Semester 2 2012-2013
Danang University of Technology, Faculty of Electronics and Telecommunications
Prepared by Ho Viet Viet, Pham Xuan Trung and Nguyen Van Hieu
Lab1: Design a MIPS 32 by 32 Register File
Due Date:
Lab Objectives:
For this lab1 you are to construct a 32 by 32 register file using Verilog HDL. The register file is introduced in chapter 4 of the class textbook. Within the 32 by 32 register file is an array of 32 different 32-bit registers. These registers must be constructed from D flip-flops (positive edge-triggered). Note that for MIPS, register zero ($zero) is hardwired to always output the value zero, regardless of what may or may not be written to it. The figure below shows a block diagram of a register file (this is a modified reproduction of figure 4.7 on page 310 of the textbook: Computer Organization and
Design 4th edition by Patterson and Hennessy).
5
Read
Register 1
5
Read
Register 2
5
Read
Data 1
32
Read
Data 2
32
Write
Register
32
Write
Data
RegWrite
Read Register 1 and Read Register 2 select the registers whose values are output on the Read Data 1 bus and Read Data 2 bus respectively. The Write Register input bus selects the target of the write; when RegWrite is true, the information on the Write Data bus register is written into that register.
Computer resources and software tools:
PCs with Software Quartus II, ModelSim, IVerilog installed, testbench file: regstim.v
Implementation:
A simple implementation of the 32 by 32 MIPS register file can be made using
Registers composed of D flip-flops, a 5:32 enabled decoder, and two large 32x32 to 32 multiplexors. This is shown in the following block diagram (note that the clock is omitted for clarity).
32
Register 1
32
Register 2
32
Decoder
Multiplexor
0
RegWrite
32
Register 31
5
Read Register 1
5
32
32
Write Data
32
32
Semester 2 2012-2013
Danang University of Technology, Faculty of Electronics and Telecommunications
Prepared by Ho Viet Viet, Pham Xuan Trung and Nguyen Van Hieu
Lab1: Design a MIPS 32 by 32 Register File
Due Date:
Lab Objectives:
For this lab1 you are to construct a 32 by 32 register file using Verilog HDL. The register file is introduced in chapter 4 of the class textbook. Within the 32 by 32 register file is an array of 32 different 32-bit registers. These registers must be constructed from D flip-flops (positive edge-triggered). Note that for MIPS, register zero ($zero) is hardwired to always output the value zero, regardless of what may or may not be written to it. The figure below shows a block diagram of a register file (this is a modified reproduction of figure 4.7 on page 310 of the textbook: Computer Organization and
Design 4th edition by Patterson and Hennessy).
5
Read
Register 1
5
Read
Register 2
5
Read
Data 1
32
Read
Data 2
32
Write
Register
32
Write
Data
RegWrite
Read Register 1 and Read Register 2 select the registers whose values are output on the Read Data 1 bus and Read Data 2 bus respectively. The Write Register input bus selects the target of the write; when RegWrite is true, the information on the Write Data bus register is written into that register.
Computer resources and software tools:
PCs with Software Quartus II, ModelSim, IVerilog installed, testbench file: regstim.v
Implementation:
A simple implementation of the 32 by 32 MIPS register file can be made using
Registers composed of D flip-flops, a 5:32 enabled decoder, and two large 32x32 to 32 multiplexors. This is shown in the following block diagram (note that the clock is omitted for clarity).
32
Register 1
32
Register 2
32
Decoder
Multiplexor
0
RegWrite
32
Register 31
5
Read Register 1
5
32
32
Write Data
32
32