Nt1310 Unit 6 Project Design Steps
PROJECT DESIGN STEPS
1. Double click the desktop Xilinx ISE icon to start XILINX ISE.
2. To create a project select File New project then give a file name as shown in figure 1 and go for next option. Figure 1: Create new project
3. New project wizard window will appear. Select options at shown as shown in figure 2 and go for Next Next Finish Figure 2: Device properties
4. In the source window right click on the device and select add source and add the written verilog code as shown in figure 3 and figure 4.
Figure 3: Selection of add source Figure 4: Adding source files
5. In process window select check syntax for checking the syntax shown in figure 5. After successful completion of check syntax generate syntax report in
1. Double click the desktop Xilinx ISE icon to start XILINX ISE.
2. To create a project select File New project then give a file name as shown in figure 1 and go for next option. Figure 1: Create new project
3. New project wizard window will appear. Select options at shown as shown in figure 2 and go for Next Next Finish Figure 2: Device properties
4. In the source window right click on the device and select add source and add the written verilog code as shown in figure 3 and figure 4.
Figure 3: Selection of add source Figure 4: Adding source files
5. In process window select check syntax for checking the syntax shown in figure 5. After successful completion of check syntax generate syntax report in