Verilog

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  • Topic: State diagram, State transition table, Nondeterministic finite state machine
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  • Published : December 16, 2012
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EE271 @ Thuy T. Le

SJSU - EE

EE271
Advanced Digital System Design & Synthesis

Short Review of Sequential Circuits
Let’s take 3 lectures to review this topic

Appendix 2: Short Review of Sequential Circuits

A.73

Overview


Sequential circuits – state value at a given time depend on the history of the applied inputs and the current inputs The history of the inputs is represented by the state of the circuit – requires storage to store the state of the circuit. All sequential circuits require feedback: Next state of the circuit to be determined from the present state and inputs. The number of states of a sequential circuit is finite and (so call Finite State Machine) Sequential circuits can be asynchronous or synchronous (clocked).









Appendix 2: Short Review of Sequential Circuits

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Appendix 2: Short Review of Sequential Circuits

1

EE271 @ Thuy T. Le

SJSU - EE

Concepts of the State Machine
Computer Hardware = Datapath + Control Control • FSM generating sequences of control signals • Instructs datapath what to do next Data inputs
State

Control signal outputs

Datapath • Storages • Combinational Functional Units (e.g., ALU) • Busses Appendix 2: Short Review of Sequential Circuits A.75

Basic Storage Components
Components: CMOS

Appendix 2: Short Review of Sequential Circuits

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Appendix 2: Short Review of Sequential Circuits

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EE271 @ Thuy T. Le

SJSU - EE

Switch and NOR

Appendix 2: Short Review of Sequential Circuits

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 

Storage elements may be clocked or unclocked. Can be level-sensitive called latches (unclocked) or edgesensitive called flip-flops (clocked) R Q R' Q'

R-S Latch (unclocked)
S Q' S' Q

S 0 0 1 1

R 0 1 0 1

Q next Q 0 1 0

Q' next Q' 1 0 0
Hold Reset Set Not Allowed

S' 0 0 1 1

R' 0 1 0 1

Q next 1 1 0 Q

Q' next 1 0 1 Q'
Not Allowed Set Reset Hold

Appendix 2: Short Review of Sequential Circuits

A.78

Appendix 2: Short Review of Sequential Circuits

3

EE271 @ Thuy T. Le

SJSU - EE

SR Q(t ) 0 1 00 0 1 01 0 0 R 11 X X

S 10 1 1

Characteristic Equation: Qnext = S + R'Q

How to enable/disable the R-S latch? • Transparent latch How to eliminate the forbidden state in R-S Latch? • Use one input to guarantee that R and S are never both one (Transparent latch) • Use output feedback to make forbidden state toggle: JK latch Appendix 2: Short Review of Sequential Circuits A.79

Transparent Latch:  Level-sensitive clock by "enable" signal) R Q' R Q EN Q S EN Q' S

D Q EN

Unstable input D leads to unstable output Q ? Solution: Use master/slave Dlatch A.80

Appendix 2: Short Review of Sequential Circuits

Appendix 2: Short Review of Sequential Circuits

4

EE271 @ Thuy T. Le

SJSU - EE

JK Latch
K R R-S latch J S Q Q Q' Q'

Characteristic Equation: Qnext = JQ' + K'Q

J 0 0 1 1

K 0 1 0 1

Qnext Q (hold) 0 (reset) 1 (set) Q’ (toggle)

Race Condition • For toggle correctness: Single state change per clocking event • Solution: Master/Slave Flip-Flop

Appendix 2: Short Review of Sequential Circuits

A.81

(Master/Slave) J-K FF • Uses time to break feedback path from outputs to inputs! – Real flip-flop (edge) if satisfying some conditions on input signals K Q' R-S Latch J S Q P S P' R R-S Latch Q Q Q'

R

Q'

Clk

Sample inputs while clock is high

Sample inputs while clock is low

• Glitch on the J or K inputs leads to a state change. This forces designer to use hazard-free logic. • Edge-triggered logic is better Appendix 2: Short Review of Sequential Circuits A.82

Appendix 2: Short Review of Sequential Circuits

5

EE271 @ Thuy T. Le

SJSU - EE

(Master/Slave Transparent) D-FlipFlop  Master samples the input during the active cycle.  The output of the master stage must settle before the enabling edge of the slave stage.  The input (D) is transferred to the output (Q) after a clock signal – Real flip-flop...
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