Reduced Instruction Set Computer
•Small number of instructions
•Instruction size constant
•Bans the indirect addressing mode
•Retains only those instructions that can be overlapped and made to execute in one machine cycle or less.
Examples of RISC
•Apple iPods (custom ARM7TDMI SoC)
•Apple iPhone (Samsung ARM1176JZF)
•Palm and PocketPC PDAs and smartphones (Intel XScale family, Samsung SC32442 - ARM9) •Nintendo Game Boy Advance (ARM7)
•Nintendo DS (ARM7, ARM9)
•Sony Network Walkman (Sony in-house ARM based chip)
•Some Nokia and Sony Ericsson mobile phones
•Emphasis on software
reduced instruction only
•Register to register:
"LOAD" and "STORE"
are independent instructions
•Low cycles per second,
large code sizes
•Spends more transistors
on memory registers
•It takes multiple instructions to perform a task that would take one instruction in a CISC processor. •RISC architectures put a greater burden on the software. Is this worth the trouble because conventional microprocessors are becoming increasingly fast and cheap anyway?
Complex Instruction Set Computer
•Large number of complex instructions
•Facilitate the extensive manipulation of low-level computational elements and events such as memory, binary arithmetic, and addressing.
Examples of CISC
•System/360(excluding the 'scientific' Model 44),
•Motorola 68000 family
•Intel x86 architecture based processors.
•Emphasis on hardware
•Includes multi-clock complex instructions
"LOAD" and "STORE” incorporated in instructions
•Small code sizes, high cycles per second
•Transistors used for storing complex instructions
•That is, the incorporation of older instruction sets into new generations of processors tended to force growing complexity. •Many specialized CISC instructions were not used frequently enough to justify their existence. •Because each CISC command must be translated by the processor into tens or even hundreds of lines of microcode, it tends to run slower than an equivalent series of simpler commands that do not require so much translation.
RISC => Effectively realizes one particular High Level Language Computer System in HW - recurring HW development costs when change needed.
CISC => Allows effective realization of any High Level Language Computer System in SW - recurring SW development costs when change needed
Harvard VS Von Neumann
Computers have separate memory areas for program instructions and data. There are two or more internal data buses, which allow simultaneous access to both instructions and data. The CPU fetches program instructions on the program memory bus.
| PROGRAM | | DATA |
| ROM | [CPU] | RAM |
A modified Harvard architecture machine is very much like a Harvard architecture machine, but it relaxes the strict separation between instruction and data while still letting the CPU concurrently access two (or more) memory buses. The most common modification includes separate instruction and data caches backed by a common address space. While the CPU executes from cache, it acts as a pure Harvard machine. When accessing backing memory, it acts like a von Neumann machine (where code can be moved around like data, a powerful technique). This modification is widespread in modern processors such as the ARM architecture and X86 processors. It is sometimes loosely called Harvard architecture, overlooking the fact that it is actually "modified". Another modification provides a pathway between the instruction memory (such as ROM or flash) and the CPU to allow words from the instruction memory to be treated as read-only data. This technique is used in some microcontrollers, including the Atmel AVR. This allows constant data, such as...