Design an 8-Bit Microprocessor Using Verilog and Verify Its Operations. Use Sap-1 (Simple as Possible) Architecture as Your Reference.
Title
Design an 8-bit microprocessor using Verilog and verify its operations. Use SAP-1 (Simple as Possible) architecture as your reference.
Introduction
The Simple-As-Possible (SAP)-1 computer is a very basic model of a microprocessor explained by Albert Paul Malvino1. The SAP-1 design contains the basic necessities for a functional Microprocessor. Its primary purpose is to develop a basic understanding of how a microprocessor works, interacts with memory and other parts of the system like input and output. The instruction set is very limited and is simple.
The features in SAP-1 computer are
W bus - A single 8 bit bus for address and data transfer.
16 Bytes memory (RAM)
Registers are accumulator and B-register each of 8 bits.
Program counter – initializes from 00H (0d) to FFH (15d) during program execution.
Memory Address Register (MAR) to store memory addresses.
Adder/ Subtracter for addition and subtraction instructions.
A Control Unit
A Simple Output.
6 machine reserved for each instruction
The instruction format of SAP-1 Computer is
(XXXX) (XXXX)
The first four bits make the op-code while the last four bits make the operand (address).
_______________________
1 Albert Paul Malvino, Ph. D. introduced the concept of SAP (Simple As Possible) computers in his book
“Digital Computer Electronics – An Introduction to Microcomputers” - 2nd Edition.
SAP-1 instruction set consists of following instructions
Mnemonic Operation Operation OPCODE
LDA Load addressed memory contents into accumulator 0000
ADD Add addressed memory contents to accumulator 0001
SUB Subtract addressed memory contents from accumulator 0010
OUT Load accumulator data into output register 1110
HLT Stop processing 1111
Example: if 0000 1000 is stored at memory location 0000 of RAM then SAP1 computer interprets it as follows:
Machine cycle and Instruction cycle
SAP1 has six T-states (three fetch and three execute cycles) reserved for each
Design an 8-bit microprocessor using Verilog and verify its operations. Use SAP-1 (Simple as Possible) architecture as your reference.
Introduction
The Simple-As-Possible (SAP)-1 computer is a very basic model of a microprocessor explained by Albert Paul Malvino1. The SAP-1 design contains the basic necessities for a functional Microprocessor. Its primary purpose is to develop a basic understanding of how a microprocessor works, interacts with memory and other parts of the system like input and output. The instruction set is very limited and is simple.
The features in SAP-1 computer are
W bus - A single 8 bit bus for address and data transfer.
16 Bytes memory (RAM)
Registers are accumulator and B-register each of 8 bits.
Program counter – initializes from 00H (0d) to FFH (15d) during program execution.
Memory Address Register (MAR) to store memory addresses.
Adder/ Subtracter for addition and subtraction instructions.
A Control Unit
A Simple Output.
6 machine reserved for each instruction
The instruction format of SAP-1 Computer is
(XXXX) (XXXX)
The first four bits make the op-code while the last four bits make the operand (address).
_______________________
1 Albert Paul Malvino, Ph. D. introduced the concept of SAP (Simple As Possible) computers in his book
“Digital Computer Electronics – An Introduction to Microcomputers” - 2nd Edition.
SAP-1 instruction set consists of following instructions
Mnemonic Operation Operation OPCODE
LDA Load addressed memory contents into accumulator 0000
ADD Add addressed memory contents to accumulator 0001
SUB Subtract addressed memory contents from accumulator 0010
OUT Load accumulator data into output register 1110
HLT Stop processing 1111
Example: if 0000 1000 is stored at memory location 0000 of RAM then SAP1 computer interprets it as follows:
Machine cycle and Instruction cycle
SAP1 has six T-states (three fetch and three execute cycles) reserved for each