Microprocessor and Interfacing

Topics: Output, Input/output, Computer Pages: 14 (3402 words) Published: March 31, 2013
UNIT II- Peripherals and Interfacing PIO 8255
The parallel input-output port chip 8255 is also called as programmable peripheral input-output port. The Intel’s 8255 is designed for use with Intel’s 8-bit, 16-bit and higher capability microprocessors. It has 24 input/output lines which may be individually programmed in two groups of twelve lines each, or three groups of eight lines. The two groups of I/O pins are named as Group A and Group B. Each of these two groups contains a subgroup of eight I/O lines called as 8-bit port and another subgroup of four lines or a 4-bit port. Thus Group A contains an 8-bit port A along with a 4-bit port. C upper.

PIO 8255
• The port A lines are identified by symbols PA0-PA7 while the port C lines are identified as PC4-PC7. Similarly, GroupB contains an 8-bit port B, containing lines PB0-PB7 and 4-bit port C with lower bits PC0- PC3.The port C upper and port C lower can be used in combination as an 8-bitport C. • Both the port C are assigned the same address. Thus one may have either three 8-bit I/O ports or two 8-bit and two 4-bit ports from 8255. All of these ports can function independently either as input or as output ports. This can be achieved by programming the bits of an internal register of 8255 called as control word register ( CWR ).

PIO 8255
• The internal block diagram and the pin configuration of 8255 are shown in fig. • The 8-bit data bus buffer is controlled by the read/write control logic. The read/write control logic manages all of the internal and external transfers of both data and control words. • RD, WR, A1, A0 and RESET are the inputs provided by the microprocessor to the READ/ WRITE control logic of 8255. The 8-bit, 3-state bidirectional buffer is used to interface the 8255 internal data bus with the external system data bus.

PIO 8255
• This buffer receives or transmits data upon the execution of input or output instructions by the microprocessor. The control words or status information is also transferred through the buffer. • The signal description of 8255 are briefly presented as follows : • PA7-PA0: These are eight port A lines that acts as either latched output or buffered input lines depending upon the control word loaded into the control word register. • PC7-PC4 : Upper nibble of port C lines. They may act as either output latches or input buffers lines.

PIO 8255
• This port also can be used for generation of handshake lines in mode 1 or mode 2. • PC3-PC0 : These are the lower port C lines, other details are the same as PC7-PC4 lines. • PB0-PB7 : These are the eight port B lines which are used as latched output lines or buffered input lines in the same way as port A. • RD : This is the input line driven by the microprocessor and should be low to indicate read operation to 8255. • WR : This is an input line driven by the microprocessor. A low on this line indicates write operation.

PIO 8255
• CS : This is a chip select line. If this line goes low, it enables the 8255 to respond to RD and WR signals, otherwise RD and WR signal are neglected. • A1-A0 : These are the address input lines and are driven by the microprocessor. These lines A1-A0 with RD, WR and CS from the following operations for 8255. These address lines are used for addressing any one of the four registers, i.e. three ports and a control word register as given in table below. • In case of 8086 systems, if the 8255 is to be interfaced with lower order data bus, the A0 and A1 pins of 8255 are connected with A1 and A2 respectively.

RD 0 0 0 0 RD 1 1 1 1 RD X 1

WR 1 1 1 1 WR 0 0 0 0 WR X 1

CS 0 0 0 0 CS 0 0 0 0 CS 1 0

A1 0 0 1 1 A1 0 0 1 1 A1 X X

A0 0 1 0 1 A0 0 1 0 1 A0 X X

Input (Read) cycle Port A to Data bus Port B to Data bus Port C to Data bus CWR to Data bus Output (Write) cycle Data bus to Port A Data bus to Port B Data bus to Port C Data bus to CWR Function Data bus tristated Data bus tristated

Control Word Register

PIO 8255.
• D0-D7 : These...
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