Uart

Only available on StudyMode
  • Topic: Interrupts, Interrupt, Programmable Interrupt Controller
  • Pages : 88 (19141 words )
  • Download(s) : 73
  • Published : December 29, 2012
Open Document
Text Preview
Section 47. Interrupts (Part V)
HIGHLIGHTS
This section of the manual contains the following major topics: 47.1 47.2 47.3 47.4 47.5 47.6 47.7 47.8 47.9 Introduction .................................................................................................................. 47-2 Non-Maskable Traps.................................................................................................... 47-7 Interrupt Processing Timing ....................................................................................... 47-12 Interrupt Control and Status Registers....................................................................... 47-15 Interrupt Setup Procedures........................................................................................ 47-65 Register Maps............................................................................................................ 47-68 Design Tips ................................................................................................................ 47-70 Related Application Notes.......................................................................................... 47-71 Revision History ......................................................................................................... 47-72

47
Interrupts (Part V)

© 2009 Microchip Technology Inc.

Preliminary

DS70597A-page 47-1

dsPIC33F Family Reference Manual
47.1 INTRODUCTION
The dsPIC33F Interrupt Controller module reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the dsPIC33F CPU. Following are the module features: • • • • • • • Up to eight processor exceptions and software traps Seven user-selectable priority levels Interrupt Vector Table (IVT) with up to 126 vectors Unique vector for each interrupt or exception source Fixed priority within a specified user priority level Alternate Interrupt Vector Table (AIVT) for debugging support Fixed interrupt entry and return latencies

47.1.1

Interrupt Vector Table

The Interrupt Vector Table (IVT) shown in Figure 47-1, resides in program memory starting at location 0x000004. The IVT contains 126 vectors consisting of eight non-maskable trap vectors and up to 118 sources of interrupt. In general, each interrupt source has its own vector. Each interrupt vector contains a 24-bit wide address. The value programmed into each interrupt vector location is the starting address of the associated Interrupt Service Routine (ISR).

47.1.2

Alternate Interrupt Vector Table

The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 47-1. Access to the AIVT is provided by the Enable Alternate Interrupt Vector Table (ALTIVT) control bit in Interrupt Control Register 2 (INTCON2). If the ALTIVT bit is set, all interrupt and exception processes use the alternate vectors instead of the default vectors. The alternate vectors are organized in the same manner as the default vectors. The AIVT supports emulation and debugging by providing a means to switch between an application and a support environment without reprogramming the interrupt vector. This feature also enables switching between applications for evaluation of different software algorithms at run time. If the AIVT is not needed, the AIVT should be programmed with the same addresses used in the IVT.

47.1.3

Reset Sequence

A device Reset is not a true exception because, the Interrupt Controller is not involved in the reset process. The dsPIC33F device clears its registers in response to a Reset, which forces the Program Counter (PC) to zero. The processor then begins program execution at location 0x000000. The user application programs a GOTO instruction at the Reset address, which redirects program execution to the appropriate start-up routine. Note: Any unimplemented or unused vector locations in the IVT and AIVT must be programmed with the address of a default interrupt handler routine that contains a RESET...
tracking img