Peripheral Component Interconnect (PCI)

Topics: Motherboard, Computer buses, Computer Pages: 10 (989 words) Published: October 13, 2013
Peripheral Component
Interconnect (PCI)

Babak Kia
Adjunct Professor
Boston University
College of Engineering

ENG SC757 - Advanced Microprocessor Design

Why PCI?
The original PC bus developed by IBM in 1982 was
16 bits wide and operated at 4.77 MHz
This was known as the ISA bus, capable of
transferring data at a whopping rate of 9 Mbytes
per second!
Gradually peripherals such as video cards and
hard drives required a higher bandwidth, and in
1992 Intel introduced the PCI bus standard to
allow connected devices direct access to the
system memory
It detached the speed of the peripheral bus from
that of the memory, so even though today’s Front
Side Buses can run up to 800 MHz, the PCI
devices can operate at their own independent
speed

What is PCI?
The Peripheral Component Interconnect is an
interconnect bus developed by Intel in 1992 which
runs at 33 MHz and supports plug-and-play
It allows high speed connection between
peripherals, and from the peripherals to the
processor
Allows for transfer of data amongst peripherals
independently of the processor
Found on many desktops, but not limited to them,
the PCI bus is a 32 bit wide bus capable of
transferring at data rates up to 132 MBytes per
second
A 66 MHz, 64-bit version is capable of transfer
rates of up to 524 Mbytes/second

1

PC System Architecture
Northbridge is the
chipset which
interfaces with
memory, PCI bus,
level 2 caches,
Accelerated Graphics
Port (AGP), on the
Front Side Bus (FSB)
Southbridge is the
chipset which handles
the basic I/O such as
USB, serial, audio,
IDE devices and ISA
bus

PC System Architecture

2

PCI Bus Signals
AD[31:0] – Multiplexed
Address/Data
C/BE[3:0]# - Command/Byte
Enable
• 0110: Memory Read
• 0111: Memory Write

PAR – Parity, always driven
as even for all AD[31:0] and
C/BE[3:0] signals
PCLK – PCI Clock, operates
from DC (0 Hz) to 33 MHz
RST# - Reset

PCI Bus Signals
FRAME# - Driven by bus
master to indicate the
beginning and duration of a
bus transaction
IRDY# - Initiator Ready,
during which AD[31:0]
contains valid data
TRDY# - Target Ready.
During read, it indicates valid
AD[31:0] data
STOP# - Conveys the
request to bus master to
stop current transaction

PCI Bus Signals
LOCK# - Provides for the
exclusive use of a resource
IDSEL – Initialization Device
Select, used as a chip select
during initialization
DEVSEL# - Device Select
INTA# - Interrupt A, driving it
low will interrupt the host
PERR# - Parity Error
SERR# - System Error,
indicates catastrophic
system error

3

Add-on Bus Signals
SCL – Serial Clock
SDA – Serial Data
MDMODE – Mailbox Data
Mode
LOAD# - Defines the MD[7:0]
signals as an input bus
MD[7:0] – Mailbox Data Bus
PTMODE – Pass-thru mode
PTATN# - Pass-thru
attention, signals a decoded
PT region
PTBURST# - Indicates
current operation is burst

Add-on Bus Signals
PTRDY#/WAIT# - PTRDY# is
asserted low to indicate add-on
logic has read/written data in
response to PTATN#
PTNUM[1:0] – Pass-thru number
PTBE[3:0]# - Pass-thru byte
enable
PTADR# - Pass-thru Address
PTWR – Indicates whether
current operation is a read or a
write
DXFR# - Transfer complete
signal

Add-on Bus Signals
DQ[31:0] – Address/Data
ADR[6:2] – Internal register
address
BE[2:0]# - Register byte
enable signals
BE3#/ADR1
SELECT# - Enables internal
logic to decode WR# and
RD# for internal register
access
WR# - Write Enable
RD# - Read Enable

4

PCI Write Example

PCI Configuration Register

Configuration Register
Every PCI device in a
system, including a PCIto-PCI bridge has a
configuration data
space.
Configuration register is
what allows the system
to identify and control
the device.
Typically systems are
designed so that every
PCI device has its
configuration register in
an offset that is related
to the slot it is at

5

Configuration Register
Vendor Identification




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