Hcl Ddr 3 Invention
AXI DDR3 Controller
The AXI DDR3 Controller provides access to DDR3 memory. It accepts the Read / Write commands from AXI and converts it into DDR3 access. While doing this it combines AXI burst transactions into single DDR access where ever possible to achieve the best possible performance from DDR3 memory subsystem.
DESCRIPTION
KEY FEATURES o High memory throughput achieved via Parallel operation of all the banks and reordering of commands in the controller to ensure the maximum utilization of the DDR Memory Pipelined operation across the complete design to ensure the highest performance DDR Interface o Supports all standard DDR3 (x4,x8,x16) SDRAMs o Supports power down modes o Run-time configurable timing parameters and memory settings o Automatic generation of initialization and refresh sequences o All burst lengths (4 & 8) supported AXI Interface o Supports AMBA 3 AXI protocol 32 bit Data Width o Does re-mapping/combines the AXI Burst transactions into memory transactions by understanding the memory architecture o Supports unaligned transactions o Supports multiple outstanding transactions o Supports delayed Writes(Independent AXI command and Data Channel )
The AXI DDR3 Controller allows access of DDR3 memory through AXI Bus interface. The controller works as an intelligent bridge between the AXI host and DDR3 memory. It takes care of the DDR initialization and various timing requirements of the DDR3 memory. The controller implements multiple schemes to increases the effective memory throughput. These schemes include combining and reordering the Read/Write commands. It operates all the memory banks in parallel for attaining the maximum throughput from the memory and minimizes the effect of precharge/refresh and other DDR internal operations.
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TECHINCAL DETAILS o Gate Count ASIC TSMC 90 nm Gate Count 34K o Clock support AXI clock 133 MHz to 400 MHz DDR3 Data Rate of 800 Mbits/Sec supported
DDR3 Controller
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The AXI DDR3 Controller provides access to DDR3 memory. It accepts the Read / Write commands from AXI and converts it into DDR3 access. While doing this it combines AXI burst transactions into single DDR access where ever possible to achieve the best possible performance from DDR3 memory subsystem.
DESCRIPTION
KEY FEATURES o High memory throughput achieved via Parallel operation of all the banks and reordering of commands in the controller to ensure the maximum utilization of the DDR Memory Pipelined operation across the complete design to ensure the highest performance DDR Interface o Supports all standard DDR3 (x4,x8,x16) SDRAMs o Supports power down modes o Run-time configurable timing parameters and memory settings o Automatic generation of initialization and refresh sequences o All burst lengths (4 & 8) supported AXI Interface o Supports AMBA 3 AXI protocol 32 bit Data Width o Does re-mapping/combines the AXI Burst transactions into memory transactions by understanding the memory architecture o Supports unaligned transactions o Supports multiple outstanding transactions o Supports delayed Writes(Independent AXI command and Data Channel )
The AXI DDR3 Controller allows access of DDR3 memory through AXI Bus interface. The controller works as an intelligent bridge between the AXI host and DDR3 memory. It takes care of the DDR initialization and various timing requirements of the DDR3 memory. The controller implements multiple schemes to increases the effective memory throughput. These schemes include combining and reordering the Read/Write commands. It operates all the memory banks in parallel for attaining the maximum throughput from the memory and minimizes the effect of precharge/refresh and other DDR internal operations.
o o
o
TECHINCAL DETAILS o Gate Count ASIC TSMC 90 nm Gate Count 34K o Clock support AXI clock 133 MHz to 400 MHz DDR3 Data Rate of 800 Mbits/Sec supported
DDR3 Controller
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