Figure 1. Mask set design. Shown is a single “mask unit cell” and its contents. Each completed 2 inch wafer contains roughly forty whole mask cells.
ECE 4752 Wafer Test Procedures
In order to evaluate the electrical characteristics of the CMOS devices fabricated in ECE/ChBE 4752, a probe station is used to connect test equipment to the devices on-wafer. This is accomplished by positioning probes with mechanical manipulators such that their tips rest on metal pads on the wafer. Care must be taken while manipulating the probes to avoid damaging the probe tips or the devices under test. The probes and wires used in the 4752 lab are suitable for relatively low-frequency and low-power measurements.
The general procedure for testing a device involves connecting suitable test equipment to probes using the banana-plug wires, landing probes on the appropriate metal pads using the microscope and probe positioners, and performing the desired measurements. If unexpected results are obtained, incorrect equipment setup or poor contact between probes and pads could be at fault. However, sometimes the device itself may be deficient due to defects in materials and processing. All relative directions described are with reference to the main unit cell orientation showed in Figure 1.
Figure 2. Layout of one of the resistor types on the mask cell.
Resistors are the simplest components on the wafer to be tested. For DC considerations, the only figure of merit of interest is the resistance, from which the resistor material resistivity can be approximated given the device dimensions. Two probes are required to test a resistor, one for each of the metal pads, which show up as large squares on either end of Figure 2. For simplicity, an ohmmeter should be used for testing the resistance, though a curve tracer could also be used. Each pad should be connected to one of the ohmmeter plugs so that a resistance measurement can be made. Each leg of the serpentine resistor pattern has a dimension of 1920×20 μm and its total linear length is 9.92 mm.
Figure 3. Layout of a MOSFET. Source, drain, gate, and body pads are labeled “S”, “D”, “G”, and “B”, respectively.
Individual transistors have numerous figures of merit which may be evaluated depending on the intended usage of the device. Of interest to nearly all transistor applications are the DC characteristics, which are typically evaluated using a curve tracer. The curve tracer biases a transistor under test at different points and measures resulting voltages and currents. One valuable set of DC characteristics for FETs measures the relationship between drain current ID and drain-to-source voltage VDS at various gate-to-source voltages VGS in common-source configuration (this is analogous to collector current versus collector-to-emitter voltage at different base currents with a common-emitter bipolar transistor). To perform this measurement, the curve tracer sweeps VDS from zero to some maximum voltage for each of a set of pre-defined values of VGS and measures the resulting drain current. Plotting this data on a graph shows the DC characteristics of the FET in several useful biasing modes (cut-off, linear/triode, and saturation). This can be used to evaluate transistor performance and to calculate several useful figures of merit--transconductance, channel-length modulation effect, saturation and breakdown voltage, etc.
Measuring DC characteristics of MOSFETs requires the use of at least three probes, and a fourth if body effects are to be taken into account. The layout of a MOSFET annotated with pad designations is shown in Figure 3. The body pad is connected to the source terminal for all of the first three nMOS and pMOS FETs from the left of the wafer cell while the fourth FET has a separate body pad which can be used if four-terminal measurements are desired.
For measurement of ID versus VDS, probes should be connected to the...
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