DIGITAL DESIGN THROUGH VERILOG

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Code No: L0422
Set No. 1
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
IV B.Tech. II Sem., I Mid-Term Examinations, Jan/Feb – 2011
DIGITAL DESIGN THROUGH VERILOG
Objective Exam
Name: ______________________________ Hall Ticket No.
A

Answer All Questions. All Questions Carry Equal Marks.Time: 20 Min. Marks: 20.

I

Choose the correct alternative:

1.

Verilog HDL is used to model
A) An Analog System
B) A Digital System

2.

3.

C) A Discrete System

[
]
D)All the above

Which of the following is not an white space character
A) \t
B) \n
C) \b

D) \s

$stop is used for
A) break point

[
D) terminate the program

B) start point

C) initial point

[

D
L

R
O

]

]

4.

To provide interface by which a module can communicate with its environment what its environment what can be used.
[
]
A) modules
B) ports
C) variables
D) none

5.

In Verilog, constants defined in a module by the keyword
A) Constant
B) Parameter
C) Const

D) None

How many logic values defined in Verilog with their strength’s
A) One
B) Two
C) Three

D) Four

6.

W
U

T
N

[

]

[

]

7.

Which of the following represents Reduction operator NOR
A) ^ ~
B) ~ |
C) ~ ^
D) |~

[

]

8.

If the input to a tranif1 bidirectional switch is supply0, then the output signal strength is [
A) weak0
B) strong0
C) weak 1
D) strong1

]

9.

Trireg nets can have _________ values
A) 0, 1, x, z
B) 0, 1, z only

]

10.

J

[
C) 0, 1, x only

D) 0, 1 only

It is legal to connect internal and external items of different ________ when making Intermodule port connections.
[
]
A) Sizes
B) Variables
C) Constants
D) None
Cont……2

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Code No: L0422

:2:

Set No. 1

II

Fill in the blanks

11.

In Verilog, with respect to gate delay’s, which delay is the minimum of all delays ___________

12.

Process of converting a high–level description of design into an optimized gate level representation is called _____________

13.

Delay associated with a gate output transition to a

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