# ECT114 week 3 lab

Topics: Logic gate, OR gate, Logic gates Pages: 5 (299 words) Published: June 1, 2014
﻿SCORE: _______/48 points

1. Using QUARTUS II software, open a new Block Diagram/Schematic file. Enter the logic gate symbols representing the following gates. Connect and label input and output pins. Label the inputs as A, B, C… and label the output as Z. Paste the schematics into this iLab. (14 points)

a. 3 input AND gate
b. 6 input OR gate
c. 2 input XOR gate
d. 4 input NAND gate
e. NOT gate
f. 8 input NOR gate
g. 2 input XNOR gate

2. Using QUARTUS II software, open a Block Diagram/Schematic file. Insert the logic gate symbol for the following Boolean expressions. Connect and label input and output pins. Paste the schematics into this iLab. (20 points)

a.
b.
c.
d.
e.

3. Analyze the switch logic circuit in Figure 1. The light ON is considered a logic HIGH, and the light OFF is considered a logic LOW.

Figure

a. Determine the truth table for the switch circuit in Figure 1. (4 points)

b. Determine the type of gate represented in Figure 1. (2 points)
And Gate
c. Sketch the output of Figure 1 based on the input waveforms shown below. Copy Figure 2 into MS-PAINT and use line draw to sketch your output then replace Figure 2 with your waveforms. (2 points)

d. Open a block diagram file in Quartus II, Insert the logic symbol from part b. Add inputs and outputs. Name the inputs SWITCH1 and SWITCH2. Label the output as LIGHT. Copy and insert your figure below. (4 points)

e. Write a technical statement describing the circuit configuration and behavior of Figure 1. Include the name of the logic circuit a written interpretation of the function table. (2 points)
The output of the __0_ gate is a logic LOW when _____When one of the two switchs are open or LOW_______
The output of the _1__ gate is a logic HIGH when __When both switchs are Closed or HIGH__________

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