Vlsi Sample Codes

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  • Topic: State diagram, Moore machine, Mealy machine
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  • Published : April 19, 2013
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Examples
Source files for examples demonstrating the use of VHDL are in the /synopsys/syn/examples/vhdl directory. The examples are Moore Machine Mealy Machine Read–Only Memory (ROM) Waveform Generator Smart Waveform Generator Definable-Width Adder-Subtracter Count Zeros — Combinational Version Count Zeros — Sequential Version Soft Drink Machine — State Machine Version Soft Drink Machine — Count Nickels Version Carry-Lookahead Adder Serial-to-Parallel Converter — Counting Bits Serial-to-Parallel Converter — Shifting Bits Programmable Logic Array (PLA)

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V3.4

VHDL Compiler Reference

Moore Machine
Figure A–1 is a diagram of a simple Moore finite-state machine. It has one input (X), four internal states (S0 to S3), and one output (Z). Figure A–1 Moore Machine Specification
0 S0 0 0 1 Present state S0 S1 S2 S3 S2 1 0 1 S3 0 1 Next state X=0 X=1 S0 S0 S2 S3 S2 S2 S3 S1 Output (Z) X=0 0 1 1 0

S1 1

1

0

The VHDL code implementing this finite-state machine is shown in Example A–1, which includes a schematic of the synthesized circuit. The machine is described with two processes. One process defines the synchronous elements of the design (state registers); the other process defines the combinational part of the design (state assignment case statement). See the discussion under ‘‘wait Statement” in Chapter 6 for more details on using the two processes.

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V3.4

VHDL Compiler Reference

Example A–1

Implementation of a Moore Machine –– Moore machine

entity MOORE is port(X, CLOCK: in BIT; Z: out BIT); end;

architecture BEHAVIOR of MOORE is type STATE_TYPE is (S0, S1, S2, S3); signal CURRENT_STATE, NEXT_STATE: STATE_TYPE; begin –– Process to hold combinational logic COMBIN: process(CURRENT_STATE,...
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