IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 4, APRIL 2012
Variation Trained Drowsy Cache (VTD-Cache): A History Trained Variation Aware Drowsy Cache for Fine Grain Voltage Scaling Avesta Sasan, Member, IEEE, Kiarash Amiri, Student Member, IEEE, Houman Homayoun, Member, IEEE, Ahmed M. Eltawil, Member, IEEE, and Fadi J. Kurdahi, Fellow, IEEE
Abstract—In this paper we present the “Variation Trained Drowsy Cache” (VTD-Cache) architecture. VTD-Cache allows for a signiﬁcant reduction in power consumption while addressing reliability issues raised by memory cell process variability. By managing voltage scaling at a very ﬁne granularity, each cache way can be sourced at a different voltage where the selection of voltage levels depends on both the vulnerability of the memory cells in that cache way to process variation and the likelihood of access to that cache location. After a short training period, the proposed architecture will micro-tune the cache, allowing signiﬁcant power reduction with negligible increase in the number of misses. In addition, the proposed architecture actively monitors the access pattern and reconﬁgures the supply voltage setting to adapt to the execution pattern of the program. The novel and modular architecture of the VTD-Cache and its associated controller makes it easy to be implemented in memory compilers with a small area and power overhead. In a case study, the SimpleScalar simulation of the proposed 32 kB cache architecture reports over 57% reduction in power consumption over standard SPEC2000 integer benchmarks while incurring an area overhead of less than 4% and an execution time penalty smaller than 1%. Index Terms—Cache, drowsy cache, fault tolerance, leakage, low power, manufacturing defects, power efﬁcient, process variation, static random access memory (SRAM), technology scaling, voltage scaling.
ECENT studies – suggest that static power consumption is on the verge of dominating dynamic power consumption for CMOS-based circuits. This phenomenon is more pronounced in static random access memory (SRAM)
Manuscript received February 12, 2010; revised June 22, 2010 and November 21, 2010; accepted December 15, 2010. Date of publication February 14, 2011; date of current version March 12, 2012. This work was supported in part by the Center for Pervasive Communications and Computing at the University of California, Irvine, Samsung Electronics Corporation under Grant SEC-43124, by the National Science Foundation under Grant ECCS-0955157, and by the National Institute of Justice, Department of Justice under Grant 2006-IJ-CXK044. A. Sasan, K. Amiri, A. M. Eltawil, and F. J. Kurdahi are with the Department of Electrical Engineering and Computer Science, University of California, Irvine, CA 92617 USA (e-mail: firstname.lastname@example.org; email@example.com; firstname.lastname@example.org; email@example.com). H. Homayoun is with the Department of Computer Science, University of California, Irvine, CA 92617 USA (e-mail: firstname.lastname@example.org). Color versions of one or more of the ﬁgures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identiﬁer 10.1109/TVLSI.2011.2106523
structures such as processor caches due to the usage of minimum sized devices and their dense structural arrangement. Furthermore, caches account for a large portion of power consumption in modern processors. Voltage scaling has long been considered as a winning solution to reduce both dynamic and leakage power consumption super linearly. However its application to memory structures requires excessive care due to reliability concerns which are exacerbated by process variation especially when operating at lower voltages. The introduced process variation widens the distribution in electrical characteristics of fabricated devices and reduces the reliability and predictability of their behavior –. Thus, the write and access time of the cache (memory...
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