V. RV64I Base Integer Instruction Set Analysis

V. RV64I Base Integer Instruction Set

A. Integer Computation Instructions
All the instructions which have been developed for the RV32I are fully supported in the RV64I ISA also. The instructions exclusive to 64-bit version are discussed here. All of these have suffix "w". Quite obviously, they produce answers consistent with their 32-bit counterparts meaning all the bits are equal from XLEN-1 to 31. These produce an error or exception when executed on RV32I.
 Integer Register-Immediate Instructions: ADDIW performs the addition of contents present in rs1 and the immediate data after padding the 12 sign bits upper. Only the 32 LSBs are stored of the result by sign extension overlooking the overflown ones.
The formatting of the instruction
The manner of operation is exactly same as explained in the Integer Register Immediate kind of instructions in the previous sub-heading. SRAW, SRLW and SLLW are the shifting instructions only for 64I which actually work 32 bits and then sign extend them to give 64.

B. Load and Store Instructions

 Load:
Being a RISC machine, it is a load and store kind of architecture and thus these instructions form an integral part of ISA. The working of LD happens as- rd is loaded with a 64-bit word from memory and then stored into rd after sign extension (if it is 64I) or without sign extension (if 32I). LW works similarly, but on a 32-bit word. LWU again works similarly but does zero extension instead of sign extension suitably. LH and LHU opearte on two bytes and LB and LBU on one byte.  Store:
The SD, SW, SH, and SB instructions store 64-bit, 32-bit, 16-bit, and 8-bit values from the low bits of register rs2 to memory. C. System Instructions
RDCYCLE is an instruction which returns the number of clock cycles into the destination register that have occurred in the processor since an arbitrary point of time. In RV64I, this will return a 64-bit unsigned integer value, which should never
REM and REMU provide the remainder of the corresponding division operation. However, if we need to obtain both the quotient and the remainder, it is recommended to write DIV instruction first followed by REM. At times, user might input divisor as zero, the answer of which is not defined and hence the ISA needs to have some provision for handling such exceptions. In RV, all the bits of quotient are set to one and the remainder is returned same as dividend in case of unsigned division. In case of overflow in signed division, quotient is returned same as dividend and the remainder is set to zero. The semantics have been tabulated as under:

Conclusion :

The project helped us get an insight into the ISA of a new processor, RISC-32VI. This processor has been kept open sourced in order to be useful for academic and research purposes.
The knowledge of MIPS architecture which was learnt in the previous semester had laid quite a good foundation and helped us understand the things. The instruction set for a 64-bit variant was also touched upon, which had minor modifications in the 32-bit variant. This ISA can be used to develop high end