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LAB 1 REPORT - Free-E CSE471

Design a MIPS 32 by 32 Register File

Group 6: 1. Le Minh Hoang 2. Le Hong Thang 3. Luong Tran Nhat Trung

Prof. Ho Viet Viet LA: Nguyen Van Hieu

Report Lab 1 – Group 6 – EE471- 09ECE

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Table of content:

       

Abstract Block Diagram Decoder module Multiplexor module Register module Regfile module Simulation result Trade-off

Report Lab 1 – Group 6 – EE471- 09ECE

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ABSTRACT:
The purpose of this design problem is to design a 32x32 register file that can write data in and read 2 ports data at the same time. The value of each register in the register file remains unchanged until the next write signal is enabled and the write data is available.

BLOCK DIAGRAM:

+ Decoder block: decoding the 5-bit signal from Write Register to choose which register is used to write the data. This block only works when the signal from RegWrite is sent to activate the block. + There are 32 register from 0 to 31, the register 0 contains only bit 0 as default. The data signal from WriteData will be sent to the chosen register from the decoder block.

Report Lab 1 – Group 6 – EE471- 09ECE

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+ Each bit from 32 register will send to the Multiplexor block and, this block will receive 32 bits from each register each time. + The Read Register 1 and 2 will choose which bit from 32 register will be read out in Read Data 1 and 2 from the Multiplexor block. + 32 register are designed from the DFF, each register has 32 bits, each bit is 1 DFF

DECODER:
+ 5-bit input and 32-bit output + Decoding to choose which register will be written WR[0] 0 0 0 0 0 0 ... 1 1 WR[1] 0 0 0 0 0 0 ... 1 1 WR[2] 0 0 0 0 1 1 ... 1 1 WR[3] 0 0 1 1 0 0 ... 1 1 WR[4] 0 1 0 1 0 1 ... 0 1 WE[0] 1 0 0 0 0 0 ... 0 0 WE[1] 0 1 0 0 0 0 ... 0 0 WE[2] 0 0 1 0 0 0 ... 0 0 WE[3] 0 0 0 1 0 0 ... 0 0 WE[4] 0 0 0 0 1 0 ... 0 0 WE[5] 0 0 0 0 0 1 ... 0 0 ... ... ... ... ... ... ... ... ... ... WE[30] 0 0 0 0 0 0 ... 1 0 WE[31] 0 0 0 0 0 0 ... 0 1

The true table of the decoder:

Code:
module decoder(WE,RegWrite,WR); output [31:0] WE; input [4:0] WR;

input RegWrite; wire notWR0,notWR1,notWR2,notWR3,notWR4; wire And01,And23,And45,And67,And89,And1011,And1213,And1415,And1617,And1819,And2021,And2223,And2425,And262 7,And2829,And3031;

not #(50) Inv0( notWR0, WR[0]); not #(50) Inv1( notWR1, WR[1]); not #(50) Inv2( notWR2, WR[2]);

Report Lab 1 – Group 6 – EE471- 09ECE

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not #(50) Inv3( notWR3, WR[3]); not #(50) Inv4( notWR4, WR[4]);

and #(50) And1 ( And01 and #(50) And2 ( And23 and #(50) And3 ( And45 and #(50) And4 ( And67 and #(50) And5 ( And89

,notWR4, notWR3, notWR2, notWR1); ,notWR4, notWR3, notWR2, WR[1] ); ,notWR4, notWR3, WR[2] , notWR1); ,notWR4, notWR3, WR[2] , WR[1] ); ,notWR4, WR[3] , notWR2, notWR1);

and #(50) And6 ( And1011,notWR4, WR[3] , notWR2, WR[1] ); and #(50) And7 ( And1213,notWR4, WR[3] , WR[2] , notWR1); and #(50) And8 ( And1415,notWR4, WR[3] , WR[2] , WR[1] ); and #(50) And9 ( And1617,WR[4] , notWR3, notWR2, notWR1); and #(50) And10( And1819,WR[4] , notWR3, notWR2, WR[1] ); and #(50) And11( And2021,WR[4] , notWR3, WR[2] , notWR1); and #(50) And12( And2223,WR[4] , notWR3, WR[2] , WR[1] ); and #(50) And13( And2425,WR[4] , WR[3] , notWR2, notWR1); and #(50) And14( And2627,WR[4] , WR[3] , notWR2, WR[1] ); and #(50) And15( And2829,WR[4] , WR[3] , WR[2] , notWR1); and #(50) And16( And3031,WR[4] , WR[3] , WR[2] , WR[1] );

and #(50) WE0 ( WE[0] , RegWrite, And01 and #(50) WE1 ( WE[1] , RegWrite, And01 and #(50) WE2 ( WE[2] , RegWrite, And23 and #(50) WE3 ( WE[3] , RegWrite, And23 and #(50) WE4 ( WE[4] , RegWrite, And45 and #(50) WE5 ( WE[5] , RegWrite, And45 and #(50) WE6 ( WE[6] , RegWrite, And67 and #(50) WE7 ( WE[7] , RegWrite, And67 and #(50) WE8 ( WE[8] , RegWrite, And89 and #(50) WE9 ( WE[9] , RegWrite, And89

, notWR0 ); , WR[0] );

, notWR0 ); , WR[0] );

, notWR0 ); , WR[0] );

, notWR0 ); , WR[0] );

, notWR0 ); , WR[0] );

and #(50)...
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