Multigate Transistors as the Future of Mosfet
REVIEW
doi:10.1038/nature10676
Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors
Isabelle Ferain1, Cynthia A. Colinge1 & Jean-Pierre Colinge1
For more than four decades, transistors have been shrinking exponentially in size, and therefore the number of transistors in a single microelectronic chip has been increasing exponentially. Such an increase in packing density was made possible by continually shrinking the metal–oxide–semiconductor field-effect transistor (MOSFET). In the current generation of transistors, the transistor dimensions have shrunk to such an extent that the electrical characteristics of the device can be markedly degraded, making it unlikely that the exponential decrease in transistor size can continue. Recently, however, a new generation of MOSFETs, called multigate transistors, has emerged, and this multigate geometry will allow the continuing enhancement of computer performance into the next decade.
T
he classic metal–oxide–semiconductor field-effect transistor
(MOSFET) is the workhorse of the microelectronics industry.
MOSFETs are the building blocks of microprocessors, memory chips and telecommunications microcircuits. A modern microprocessor can contain more than 2 billion MOSFETs, and a 32-gigabyte memory card weighing only 0.5 g contains a staggering 256 billion transistors, which is comparable to the number of stars in the Milky Way. MOSFETs are mainly used as switches in logic microcircuits, although they can fulfil other purposes.
A textbook example of a MOSFET is shown in Fig. 1a. The device consists of two n-type semiconductor regions called the source and the drain, which are separated by a region of p-type semiconductor called the substrate. This description is for an n-channel MOSFET, or NMOS device.
A p-type MOSFET, or PMOS device, would have the opposite doping in the source, drain and substrate regions. Typically, the semiconductor
is
doi:10.1038/nature10676
Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors
Isabelle Ferain1, Cynthia A. Colinge1 & Jean-Pierre Colinge1
For more than four decades, transistors have been shrinking exponentially in size, and therefore the number of transistors in a single microelectronic chip has been increasing exponentially. Such an increase in packing density was made possible by continually shrinking the metal–oxide–semiconductor field-effect transistor (MOSFET). In the current generation of transistors, the transistor dimensions have shrunk to such an extent that the electrical characteristics of the device can be markedly degraded, making it unlikely that the exponential decrease in transistor size can continue. Recently, however, a new generation of MOSFETs, called multigate transistors, has emerged, and this multigate geometry will allow the continuing enhancement of computer performance into the next decade.
T
he classic metal–oxide–semiconductor field-effect transistor
(MOSFET) is the workhorse of the microelectronics industry.
MOSFETs are the building blocks of microprocessors, memory chips and telecommunications microcircuits. A modern microprocessor can contain more than 2 billion MOSFETs, and a 32-gigabyte memory card weighing only 0.5 g contains a staggering 256 billion transistors, which is comparable to the number of stars in the Milky Way. MOSFETs are mainly used as switches in logic microcircuits, although they can fulfil other purposes.
A textbook example of a MOSFET is shown in Fig. 1a. The device consists of two n-type semiconductor regions called the source and the drain, which are separated by a region of p-type semiconductor called the substrate. This description is for an n-channel MOSFET, or NMOS device.
A p-type MOSFET, or PMOS device, would have the opposite doping in the source, drain and substrate regions. Typically, the semiconductor
is
Links: 2010ITRS/2010Update/ToPost/2010Tables_ORTC_ITRS.xls〉 (2010). SQWIRE under Grant Agreement No. 257111 and the European Community (EC) Seventh Framework Program through the Network of Excellence Nano-TEC under