Digital Design Flow Options
DIGITAL DESIGN FLOW OPTIONS
A Thesis Presented in Partial Fulfillment of the Requirements for the Degree Master of Science in the Graduate School of The Ohio State University
By Sagar Vidya Reddy, B.E. ***** The Ohio State University 2001
Master’s Examination Committee: Professor. Joanne E. DeGroat, Adviser Professor. Steven B. Bibyk
Approved by
Adviser Department of Electrical Engineering
ABSTRACT
VLSI (Very Large Scale Integration) IC design flow is a term used to describe the process of chip design. The circuit designer/design group uses a multitude of computer aided design tools throughout the design flow to tape out an integrated circuit IC. There are numerous computer aided design (CAD) tools available commercially to help such designers in design. The design tools and the order in which they are used is termed as the design flow. CAD tools however do have certain problems associated with them. Cost, accessibility, compatibility and reliability are a few of such problems. At the university level, usability, tutorials and adequate documentation is needed to facilitate students to adapt and familiarize themselves with the CAD tool suites in a short time. In mixed signal chips, there are two distinct phases of design, the analog and the digital part. The analog part of the chip (probably containing a few hundred ii
transistors) consumes a considerable amount of time to design. The digital part of the chip (probably containing tens of thousands to a million transistors) needs to be developed in a relatively short period of time. Thus design team needs to place a few thousand gates quickly and reliably. To support this, the choice of CAD tools becomes critical. A good CAD tool can drastically reduce the time required to design a large digital block. The scope of this thesis is to search for an optimal digital design flow. The aim is to use a set of commercial and open sourced tools and bring digital logic design to such a stage that the
A Thesis Presented in Partial Fulfillment of the Requirements for the Degree Master of Science in the Graduate School of The Ohio State University
By Sagar Vidya Reddy, B.E. ***** The Ohio State University 2001
Master’s Examination Committee: Professor. Joanne E. DeGroat, Adviser Professor. Steven B. Bibyk
Approved by
Adviser Department of Electrical Engineering
ABSTRACT
VLSI (Very Large Scale Integration) IC design flow is a term used to describe the process of chip design. The circuit designer/design group uses a multitude of computer aided design tools throughout the design flow to tape out an integrated circuit IC. There are numerous computer aided design (CAD) tools available commercially to help such designers in design. The design tools and the order in which they are used is termed as the design flow. CAD tools however do have certain problems associated with them. Cost, accessibility, compatibility and reliability are a few of such problems. At the university level, usability, tutorials and adequate documentation is needed to facilitate students to adapt and familiarize themselves with the CAD tool suites in a short time. In mixed signal chips, there are two distinct phases of design, the analog and the digital part. The analog part of the chip (probably containing a few hundred ii
transistors) consumes a considerable amount of time to design. The digital part of the chip (probably containing tens of thousands to a million transistors) needs to be developed in a relatively short period of time. Thus design team needs to place a few thousand gates quickly and reliably. To support this, the choice of CAD tools becomes critical. A good CAD tool can drastically reduce the time required to design a large digital block. The scope of this thesis is to search for an optimal digital design flow. The aim is to use a set of commercial and open sourced tools and bring digital logic design to such a stage that the