8-Bit, Microprocessor-Compatible, A/D
The ADC080X family are CMOS 8-Bit, successiveapproximation A/D converters which use a modified potentiometric ladder and are designed to operate with the
8080A control bus via three-state outputs. These converters
appear to the processor as memory locations or I/O ports,
and hence no interfacing logic is required.
The differential analog voltage input has good commonmode-rejection and permits offsetting the analog zero-inputvoltage value. In addition, the voltage reference input can be adjusted to allow encoding any smaller analog voltage span
to the full 8 bits of resolution.
Typical Application Schematic
• 80C48 and 80C80/85 Bus Compatible - No Interfacing
• Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . 1kΩ). If input bypass capacitors are necessary for noise filtering and high source resistance is desirable to
minimize capacitor size, the effects of the voltage drop across this input resistance, due to the average value of the input current, can be compensated by a full scale adjustment while the given source resistor and input bypass capacitor are both in place. This is possible because the average value of the
input current is a precise linear function of the differential input voltage at a constant conversion rate.
( 5 × 10 ) ( 640 × 10 )
V PEAK = --------------------------------------------------------- ≅ 1.9V . ( 6.28 ) ( 60 ) ( 4.5 )
The allowed range of analog input voltage usually places
more severe restrictions on input common-mode voltage
levels than this.
An analog input voltage with a reduced span and a relatively large zero offset can be easily handled by making use of the differential input (see Reference Voltage Span Adjust).
Analog Input Current
The internal switching action causes displacement currents to flow at the analog inputs. The voltage on the on-chip
capacitance to ground is switched through the analog
differential input voltage, resulting in proportional currents entering the VIN(+) input and leaving the VIN(-) input. These current transients occur at the leading edge of the internal clocks. They rapidly decay and do not inherently cause errors as the on-chip comparator is strobed at the end of the clock perIod.
Input Bypass Capacitors
Bypass capacitors at the inputs will average these charges
and cause a DC current to flow through the output resistances of the analog signal sources. This charge pumping action is
worse for continuous conversions with the VIN(+) input voltage at full scale. For a 640kHz clock frequency with the VIN(+)
The leads to the analog inputs (pins 6 and 7) should be kept as short as possible to minimize stray signal pickup (EMI).
Both EMI and undesired digital-clock coupling to these inputs can cause system errors. The source resistance for these
inputs should, in general, be kept below 5kΩ. Larger values of source resistance can cause undesired signal pickup. Input
bypass capacitors, placed from the analog inputs to ground,
will eliminate this pickup but can create analog scale errors as these capacitors will average the transient input switching
currents of the A/D (see Analog Input Current). This scale
error depends on both a large source resistance and the use
of an input bypass capacitor. This error can be compensated
by a full scale adjustment of the A/D (see Full Scale
Adjustment) with the source resistance and input bypass
capacitor in place, and the desired conversion rate.
Reference Voltage Span Adjust
For maximum application flexibility, these A/Ds have been
designed to accommodate a 5V, 2.5V or an adjusted voltage
reference. This has been achieved in the design of the IC as shown in Figure 12.
Notice that the reference voltage for the IC is either 1/2 of the voltage which is applied to the V+ supply pin, or is equal to the voltage...