Instruction Cycle

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Table of Contents
Basic Computing Systems Organization…………………………………………………………………3 Instruction Cycle…………………………………………………………………………………………..3

The Fetch-Decode-Execute Cycle……..………………………........…………………………………….4

Fetch Cycle………………………………………………………………………...………………………5

Decode Cycle………………………………………………………………………………………………6

Execute Cycle……………………………………………………………………………………..….……7

System Buses……………………………………………………………………………………….…..….8

Registers……………………………………………………………………………………………...……9

Clocks………………………………………………………….…………………………………………...9

Appendix………………………………………………………………………………….……………….10

References……………………………………………….………………………………………………...11

1

BASIC COMPUTING SYSTEMS ORGANIZATION

INSTRUCTION CYCLE
An instruction cycle (fetch-and-execute cycle, fetch-decode-execute cycle, or FDX) is the basic operation cycle of a computer. It is the process by which a computer retrieves a program instruction from its memory, determines what actions the instruction requires, and carries out those actions. This cycle is repeated continuously by the central processing unit(CPU), from boot up to when the computer is shut down.

FETCH INSTRUCTION

DECODE INSTRUCTION

EXECUTE INSTRUCTION

2

THE FETCH-DECODE-EXECUTE CYCLE

Von Neumann architecture (e.g. Pentium is using an von Neumann architecture for the external memory), which – – – Allows instructions and data to be mixed and stored in the same memory module More flexible and easier to implement Suitable for most of the general purpose processors

The fetch-decode-execute cycle represents the steps that a computer follows to run a program. The CPU fetches an instruction (transfers it from main memory to the instruction register), decodes it (determines the op-code and fetches any data necessary to carry out the instruction), and executes it (performs the operation(s) indicated by the instruction). A large part of this cycle is spent copying data from one location to another. When a program is initially loaded, the address of the first instruction must be placed in the PC. The steps in this cycle, which take place in specific clock cycles, are listed below. Fetch Phase: ♦ Copy the contents of the PC to the MAR: MAR ¬ PC. ♦ Go to main memory and fetch the instruction found at the address in the MAR, placing this instruction in the IR; increment PC by 1 (PC now points to the next instruction in the program): IR ¬ M[MAR] and then PC ¬ PC+1. (Note: Because MARIE is word-addressable, the PC is incremented by one, which results in the next word's address occupying the PC. If MARIE were byte-addressable, the PC would need to be incremented by 2 to point to the address of the next instruction, because each instruction would require two bytes. On a byte-addressable machine with 32-bit words, the PC would need to be incremented by 4.) Decode Phase: ♦ Copy the rightmost 12 bits of the IR into the MAR; decode the leftmost four bits to determine the opcode, MAR ¬ IR[11–0], and decode IR[15–12]. Execute Phase: ♦ If necessary, use the address in the MAR to go to memory to get data, placing the data in the MBR (and possibly the AC), and then execute the instruction MBR ¬ M[MAR] and execute the actual instruction.

3 Instruction Cycle

FETCH CYCLE

0100

Address Bus

MOV AX,0

0100 0102

Data Bus

Instruction Pointer General Purpose Register AX

Decode Unit

Execute Unit Instruction Register

• • •

In the first phase, the processor generates the necessary timing signals to fetch the next instruction from the memory system. The instruction is transferred from memory to an internal location inside the processor (the instruction register) In the above image, the processor is ready to begin the Fetch cycle. The current contents of the instruction counter (program counter) is address 0100. This value is placed on the address bus, and a READ signal is activated on the control bus. The memory receives this and finds the contents of the memory location 0100, which happens to...
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