Pipelining

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Pipelining
• Principles of pipelining
• Simple pipelining
• Structural Hazards
• Data Hazards
• Control Hazards
• Interrupts
• Multicycle operations
• Pipeline clocking

© 1998 by Hill, Wood, Sohi,
Smith and Vijaykumar and
Moshovos

ECE D52 Lecture Notes: Chapter 3

1

Sequential Execution Semantics
We will be studying techniques that exploit the semantics of Sequential Execution.
Sequential Execution Semantics:
instructions appear as if they executed in the program specified order and one after the other
Alternatively
At any given point in time we should be able to identify an instruction so that:
1. All preceding instructions have executed
2. None following has executed

© 1998 by Hill, Wood, Sohi,
Smith and Vijaykumar and
Moshovos

ECE D52 Lecture Notes: Chapter 3

2

Exploiting Sequential Semantics
• The “it should appear” is the key
• The only way one can inspect execution order is via the
machine’s state
This includes registers, memory and any other named storage
We will looking at techniques that relax execution order while preserving sequential execution semantics

© 1998 by Hill, Wood, Sohi,
Smith and Vijaykumar and
Moshovos

ECE D52 Lecture Notes: Chapter 3

3

Steps of Instruction Execution
Instruction execution is not a
monolithic action

Fetch
Decode

There are multiple microactions involved

Read Operands
Operation
Writeback Result
Determine Next Instruction
© 1998 by Hill, Wood, Sohi,
Smith and Vijaykumar and
Moshovos

ECE D52 Lecture Notes: Chapter 3

4

Pipelining: Partially Overlap Instructions
Unpipelined

time

1/Throughput

instructions
latency

Pipelined

1/Throughput

time
instructions
latency

Time sequential
Ideally: Time pipeline = ----------------------------------------PipelineDepth

This ignores fill and drain times
© 1998 by Hill, Wood, Sohi,
Smith and Vijaykumar and
Moshovos

ECE D52 Lecture Notes: Chapter 3

5

Sequential Semantics Preserved?
a

b

Time
fetch I4

decode I4

r0 = r0 + r2

fetch I5

decode I5

r1 = r1 + 1

in-progress

fetch I6

decode I6

r3 = r1 != 10

committed

in-progress

Two execution states:
1. In-progress: changes not visible to outsiders
2. Committed: changes visible
© 1998 by Hill, Wood, Sohi,
Smith and Vijaykumar and
Moshovos

ECE D52 Lecture Notes: Chapter 3

6

Principles of Pipelining: Example
Overlap

Pick Longest Stage

Critical Path Determines Clock Cycle

© 1998 by Hill, Wood, Sohi,
Smith and Vijaykumar and
Moshovos

ECE D52 Lecture Notes: Chapter 3

7

Principles of Pipelining: Ideal Case
Let T be the time to execute an instruction
t
Instruction execution requires n stages, t1...tn taking T = ∑ i 1
1
1
W/O pipelining: TR = -- = ----- Latency = T = ------T
TR
t
∑i
n
1
------------------ ≤--W/ n-stage pipeline: TR =
max(t i) T

Latency = n × max(t i) ≥ T
t
∑i

Speedup = ------------------ ≤n
max(t i)

If all ti are equal, Speedup is n
Ideally: Want higher Performance? Use more pipeline stages
© 1998 by Hill, Wood, Sohi,
Smith and Vijaykumar and
Moshovos

ECE D52 Lecture Notes: Chapter 3

8

Pipelining Limits
• After a certain number of stages benefits level off and later they start diminishing
• Pipeline Utility is limited by:
1. Implementation
a. Logic Delay
b. Clock Skew
c. Latch Delay
2. Structures
3. Programs
2 & 3 will be called HAZARDS
© 1998 by Hill, Wood, Sohi,
Smith and Vijaykumar and
Moshovos

ECE D52 Lecture Notes: Chapter 3

9

Pipeline Limits: #1 Logic Delay

latch

latch

• tl = logic block’s worst case
delay
logic

• T = clock period
T >= tl
• Today’s Procs:

clock

clock
computation starts

6-12 2-input gates per stage

should complete before this

tl

T
© 1998 by Hill, Wood, Sohi,
Smith and Vijaykumar and
Moshovos

ECE D52 Lecture Notes: Chapter 3

10

Pipelining Limits: #2 Clock Skew
stage
i...
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