Digital Logic Assignment - Signed Multiplication
ASSIGNMENT
Instructions:
The design tasks of this assignment are to be done in pairs. However, each student must write his/her own VHDL codes, simulation work and submit an individual report. Reports must be printed / written NEATLY.
Deadline:
21st January 2010 (Friday, week 13) by 4pm. Submit to Ms Lee YL (BR4027)
Signed multiplication can be performed with either a negative multiplicand or multiplier represented in 2’s complement by summation of partial product of the multiplicand and all the bits of the multiplier except the most significant bit (MSB), which is subtracted from the partial sum instead. As an example, 3 × –4 (represented by n=4 bits) are computed as follows:
0011 × 1100:
0 0 0 0 0011 × 0 0 0 0 0 0011 × 0 0 0 1 1 + 0011 × 1 0 0 1 1 0 0 0 0 1 1 – 0011 × 1 1 1 1 0 1 0 0 (product is –12, represented in 2’s complement)
A RISC machine performs the above-described signed integer multiplication of n by n bits using a multiplier with the following components:
1. An n-bit register stores the multiplicand. 2. An n-bit right-shift register stores the multiplier. 3. A 2n-bit accumulator shift register stores the product 4. An n+1-bit 2’complement adder 5. A counter to count the bits of the multiplier
The procedures to perform a 2’s complement multiply are as follows:
1. Bit counter and product accumulator register are cleared. 2. Add product of the multiplicand and rightmost bit of multiplier. 3. Shift accumulator register and multiplier register right 1 bit. 4. Decrement counter and repeat from step 2 if count is less than n – 1. 5. Subtract the product of the multiplicand and bit n – 1 of the multiplier.
Tasks:
a) Draw an ASM chart for the multiplier
b) Design the datapath.
c) Design the hardwired control unit using one flip-flop per state technique.
d) Write the VHDL code for your design.
e)
Instructions:
The design tasks of this assignment are to be done in pairs. However, each student must write his/her own VHDL codes, simulation work and submit an individual report. Reports must be printed / written NEATLY.
Deadline:
21st January 2010 (Friday, week 13) by 4pm. Submit to Ms Lee YL (BR4027)
Signed multiplication can be performed with either a negative multiplicand or multiplier represented in 2’s complement by summation of partial product of the multiplicand and all the bits of the multiplier except the most significant bit (MSB), which is subtracted from the partial sum instead. As an example, 3 × –4 (represented by n=4 bits) are computed as follows:
0011 × 1100:
0 0 0 0 0011 × 0 0 0 0 0 0011 × 0 0 0 1 1 + 0011 × 1 0 0 1 1 0 0 0 0 1 1 – 0011 × 1 1 1 1 0 1 0 0 (product is –12, represented in 2’s complement)
A RISC machine performs the above-described signed integer multiplication of n by n bits using a multiplier with the following components:
1. An n-bit register stores the multiplicand. 2. An n-bit right-shift register stores the multiplier. 3. A 2n-bit accumulator shift register stores the product 4. An n+1-bit 2’complement adder 5. A counter to count the bits of the multiplier
The procedures to perform a 2’s complement multiply are as follows:
1. Bit counter and product accumulator register are cleared. 2. Add product of the multiplicand and rightmost bit of multiplier. 3. Shift accumulator register and multiplier register right 1 bit. 4. Decrement counter and repeat from step 2 if count is less than n – 1. 5. Subtract the product of the multiplicand and bit n – 1 of the multiplier.
Tasks:
a) Draw an ASM chart for the multiplier
b) Design the datapath.
c) Design the hardwired control unit using one flip-flop per state technique.
d) Write the VHDL code for your design.
e)