Design Exchange of the Single Chip Multi-Computer Networks

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“DESIGN EXCHANGE OF THE SINGLE CHIP MULTI-COMPUTER NETWORKS” Abstract
Submitted in Partial fulfillment of the requirement for the degree of DOCTOR OF PHILOSOPHY
IN
COMPUTER SCIENCE
by
Chandra Shekhar
Enrollment No:- ____________
Under the Supervision of
Dr. Mohammad Hussain
Professor, AIET,
Lucknow

COMPUTER SCIENCE
Sai Nath University
Ranchi, Jharkhand
Year of Submission: ______

Introduction
A recent trend in high performance computing (HPC) has been towards the use of parallel processing to solve computationally-intensive problems. Several parallel architectures, which offer corresponding increases in performance as the number of processors is increased, have been designed in the last few years. Nowadays, with the enormous transistor budgets of 45-nm and 32- nm technologies on a silicon die, it is feasible to place large CPU clusters on a single chip (System on Chip, SoC) allowing both large local memories and the high bandwidth of on-chip interconnection. Using this chip-scale multiprocessing, the number of processors on a chip may in the near future scale to dozens or hundreds, depending on their complexity. The basic requirement for building such a SoC turned out to be the low power consumption, in order that system parts could be close together and communication time would be thus minimized. For the same reason, the CPU cores should be simple and processing nodes should be interconnected as effectively as possible. Buses and point-to-point connections are the main means to connect the components. Buses can efficiently connect 3-10 communication partners but they do not scale to higher numbers. Even worse‚ they behave very unpredictably, as seen from an individual component‚ because many other components also use them. A second problem comes from the physics of deep submicron technology. Long‚ global wires and buses become undesirable due to tight timing constraints and skew control‚ high power consumption and noise phenomenon. As a consequence‚ in 1999 several research groups started to investigate systematic approaches to the design of the communication part of SoCs. This research area has been called Network on Chip (NoC). A NoC is constructed from multiple point-to-point data links interconnected by switches (routers), so that messages can be relayed from any source module to any destination module over several links by making routing decisions at the switches. Although NoCs can borrow concepts and techniques from the well-established domain of computer networking, it is impractical to blindly reuse features of "classical" computer networks and symmetric multiprocessors. In particular, NoC switches should be small, energy-efficient, and fast. The routing algorithms should be implemented by a simple logic, and the number of data buffers should be minimal. These requirements have converged on the use of pipelined, distance-insensitive wormhole (WH) message switching and source-based routing algorithms. 1. 1 Interconnection Networks

Digital electronic systems of all types are rapidly becoming communication limited. Movement of data, not arithmetic or control logic, is the factor limiting cost, performance, size and power in these systems. At the same time, buses, long the mainstay of system interconnect, are unable to keep up with increasing performance requirements. Interconnection networks offer an attractive solution to this communication crisis and are becoming pervasive in digital systems. A well-designed interconnection network makes efficient use of scarce communication resources - providing high-bandwidth, low-latency communication between clients with a minimum of cost and energy. 1.1.1 Network Basics

In order to meet the performance specifications of a particular application, the network designer must work within topology constraints to implement the topology, routing and flow control of the network. A key to the efficiency of interconnection networks comes from the fact that...
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