Design Exchange of the Single Chip Multi-Computer Networks
“DESIGN EXCHANGE OF THE SINGLE CHIP MULTI-COMPUTER NETWORKS”
Abstract
Submitted in Partial fulfillment of the requirement for the degree of
DOCTOR OF PHILOSOPHY
IN
COMPUTER SCIENCE by Chandra Shekhar
Enrollment No:- ____________
Under the Supervision of
Dr. Mohammad Hussain
Professor, AIET,
Lucknow
COMPUTER SCIENCE
Sai Nath University
Ranchi, Jharkhand Year of Submission: ______
Introduction
A recent trend in high performance computing (HPC) has been towards the use of parallel processing to solve computationally-intensive problems. Several parallel architectures, which offer corresponding increases in performance as the number of processors is increased, have been designed in the last few years. Nowadays, with the enormous transistor budgets of 45-nm and 32- nm technologies on a silicon die, it is feasible to place large CPU clusters on a single chip (System on Chip, SoC) allowing both large local memories and the high bandwidth of on-chip interconnection. Using this chip-scale multiprocessing, the number of processors on a chip may in the near future scale to dozens or hundreds, depending on their complexity. The basic requirement for building such a SoC turned out to be the low power consumption, in order that system parts could be close together and communication time would be thus minimized. For the same reason, the CPU cores should be simple and processing nodes should be interconnected as effectively as possible.
Buses and point-to-point connections are the main means to connect the components. Buses can efficiently connect 3-10 communication partners but they do not scale to higher numbers. Even worse‚ they behave very unpredictably, as seen from an individual component‚ because many other components also use them. A second problem comes from the physics of deep submicron technology. Long‚ global wires and buses become undesirable due to tight timing constraints and skew control‚ high power consumption and noise phenomenon.
As a
Abstract
Submitted in Partial fulfillment of the requirement for the degree of
DOCTOR OF PHILOSOPHY
IN
COMPUTER SCIENCE by Chandra Shekhar
Enrollment No:- ____________
Under the Supervision of
Dr. Mohammad Hussain
Professor, AIET,
Lucknow
COMPUTER SCIENCE
Sai Nath University
Ranchi, Jharkhand Year of Submission: ______
Introduction
A recent trend in high performance computing (HPC) has been towards the use of parallel processing to solve computationally-intensive problems. Several parallel architectures, which offer corresponding increases in performance as the number of processors is increased, have been designed in the last few years. Nowadays, with the enormous transistor budgets of 45-nm and 32- nm technologies on a silicon die, it is feasible to place large CPU clusters on a single chip (System on Chip, SoC) allowing both large local memories and the high bandwidth of on-chip interconnection. Using this chip-scale multiprocessing, the number of processors on a chip may in the near future scale to dozens or hundreds, depending on their complexity. The basic requirement for building such a SoC turned out to be the low power consumption, in order that system parts could be close together and communication time would be thus minimized. For the same reason, the CPU cores should be simple and processing nodes should be interconnected as effectively as possible.
Buses and point-to-point connections are the main means to connect the components. Buses can efficiently connect 3-10 communication partners but they do not scale to higher numbers. Even worse‚ they behave very unpredictably, as seen from an individual component‚ because many other components also use them. A second problem comes from the physics of deep submicron technology. Long‚ global wires and buses become undesirable due to tight timing constraints and skew control‚ high power consumption and noise phenomenon.
As a