Design Review Process Ver 0.2
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Revi sion A Date 5/15/2006 Written By Venkat Vedam Initial release Comments
This document is intended to detail the document review process for RTL based designs done for ASIC based products. It will be enhanced over time to include additional features and concerns. The purpose of the design review is to make sure that the module is designed to be free from defects, meet the intended requirements, have proper architecture and implementation methods used. This design review process is also intended to insure that other team members understand the operation of the design. The design review should be done at the AFE date of the module.
Target Audience: • Architects. • Designers • Verification – unit and system • DFT Required participants: • Module/Submodule architect • Verification representative • Design manager • Senior designer • Implementation team – TE/Synth/Timing.
• The designer should have the following complete prior to the design review: Design o Must be checked into the repository. o At All Function Entered (AFE) with some level of unit testing complete. Engineering spec detailing following: (see engineering spec template for full list) o Requirements/features/functions of the module o Block diagram of the implementation o Reset requirements - types, control o Clocking requirements – types, restrictions, gating used, async domains o DFT requirements – Above ordinarily o Brief description of the I/Os of the modules. o List of rams/roms used in module Customer spec (initial draft) detailing following o Registers and bit definitions Spyglass reports for resets and async domains Lint report detailing open lint warnings and errors.
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Completed RTL review checklist. (appendix A)
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