VLSI IMPLEMENTATION OF ARRAY BASED FIR FILTER FOLDING
A PROJECT REPORT
Submitted by POORNIMA.K (41502106067) REKHA.H (41502106084) SARADA VINAYAK (41502106090)
in partial fulfillment for the award of the degree of BACHELOR OF ENGINEERING in ELECTRONICS AND COMMUNICATION ENGINEERING
SRM ENGINEERING COLLEGE, KATTANKULATHUR ANNA UNIVERSITY:: CHENNAI 600 025 APRIL 2006
ANNA UNIVERSITY : CHENNAI 600 025
Certified that this project report “VLSI IMPLEMENTATION OF ARRAY BASED FIR FILTER FOLDING” is the bonafide work of POORNIMA.K (41502106067), REKHA.H (41502106084) SARADA VINAYAK (41502106090) who carried out the project work under my supervision.
SIGNATURE DR.S.JAYASHRI HEAD OF THE DEPARTMENT
SIGNATURE MR.J.SELVAKUMAR SUPERVISOR LECTURER
ELECTRONICS AND COMMUNICATION ENGG. SRM Engineering College SRM nagar Kattankulathur Kancheepuram 603203
ELECTRONICS AND COMMUNICATION ENGG. S.R.M Engineering College SRM nagar Kattankulathur Kancheepuram 603203
INTERNAL EXAMINER ACKNOWLEDGMENT
We express our sincere thanks to the Chairman, Thiru.T.R.Pachamuthu, the Director, Mr.T.P.Ganesan, and the management. We are grateful to our Principal, Prof.K.Venkataramani for his support and direction in the course of the project.
We take great pleasure in thanking our Head of the Department, Dr.S.Jayashri who has always been a source of inspiration. Her constant motivation has been a driving force for the successful completion of the project.
This project was made possible due to the proficient and prompt guidance given by our Project Guide, Mr.J.Selvakumar. We take this opportunity to express our gratitude for the encouragement he has provided us. We are indebted to him for spending his valuable time with us.
We thank our project coordinator, Mrs.M.Susila for conducting periodic reviews and giving us valuable suggestions. We also thank the lab technicians for their help and cooperation.
This project aims to implement finite impulse response (FIR) filter based on multiplier arrays in Very Large Scale Integration (VLSI) and intends to show the reduction of the hardware complexity that result out of folding techniques.
FIR filter being one of the fundamental components of digital signal processing (DSP) has a vital role to play in communication and signal processing. The advantages of FIR filter are stability and easy implementation but these are undermined by its hardware complexity due to large number of filter-taps. Thus, processes such as folding are used to reduce the hardware complexity of FIR filters because they involve repetitive multiplications.
This project deals with the implementation of an 8 tap FIR filter in unfolded, folded and two-stage cascaded folded filter. Cascading combines the merits of folded and unfolded schemes. The filters are implemented with four multipliers- Braun array, Ripple carry, carry save and Wallace tree. The performance of the structures with the four multipliers is compared in terms of hardware complexity and combinational path delay.
The advantages of VLSI such as low cost, low power, high reliability, small size and high functionality are to be exploited in this project. The hardware descriptive language used is verilog HDL. TABLE OF CONTENTS
ABSTRACT LIST OF TABLES LIST OF FIGURES LIST OF SYMBOLS AND ABBREVIATIONS
iv x xi
DIGITAL SIGNAL PROCESSING 1.1.1 Analog and digital signals 1.1.2 Signal processing 1.1.3 Digital signal processors 1.1.4 Applications of DSP
1 1 1 2 2
LITERATURE OVERVIEW 2.1 2.2 2.3 FILTERS ANALOG FILTERS DIGITAL FILTERS 2.3.1 Advantages of digital filter 2.3.2 Operation of digital filter 2.3.3 FIR and IIR filters 2.3.4 FIR filter 188.8.131.52 Terms used in FIR filter
4 4 4 4 5 6 7 7 7
184.108.40.206 Advantages of FIR filter 220.127.116.11 Disadvantages of FIR filter 2.4 FOLDING
8 9 9
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