Technical Terms Used in Vlsi (Semi Conductor Design)
Hardware Design
Some Important terms:
1) HDL: Hardware Description Language
e.g. VHDL and Verilog
This is the language in which the design is coded. The design code is in a specific format called RTL design.
2) RTL: Register Transfer Logic
The way the design is coded.
2a) flip flop: One unit for 1 memory retention.
3) Test bench: This is the program that tests the design. It applies the stimulus to the design and compares the actual output with the expected output. If the actual output is same as the expected output then the test case passes i.e the functionality is correct. If the actual output is different then the expected output then there is a bug which has to be fixed by the designer of the module which is not behaving the way it should. The expected output is obtained by applying the test case to the C model of the ASIC.
3 a) HVL: Hardware Verification Language
The testbench required to test the RTL design is coded using HVL. Examples are (VERA, e language and system C).
The complex testbenches like the full chip verification is normally written in HVL.
Prior to the use of HVL, HDLs were used to write the simple testbenches. As the complexity of testbench increases with the increase in the design and functionality HVL are being used to write complex testbenches.
4) Module level Verification:
Each RTL designer codes his module/ modules. He writes a small testbench to test his module so that the bugs caught are fixed at the module level. This verification is called module level verification
5) Chip level Verification
Once all the module are tested separately then One engineer with integrate all the modules into chip level design. This chip level design it tested by instantiated it in the chip level verification environment. This environment can be coded in VERA, E language and /or system C or system verilog.
The verification is an iterative process where the testcases are applied and the response viewed. Incase any bug then the bug is fixed in
Some Important terms:
1) HDL: Hardware Description Language
e.g. VHDL and Verilog
This is the language in which the design is coded. The design code is in a specific format called RTL design.
2) RTL: Register Transfer Logic
The way the design is coded.
2a) flip flop: One unit for 1 memory retention.
3) Test bench: This is the program that tests the design. It applies the stimulus to the design and compares the actual output with the expected output. If the actual output is same as the expected output then the test case passes i.e the functionality is correct. If the actual output is different then the expected output then there is a bug which has to be fixed by the designer of the module which is not behaving the way it should. The expected output is obtained by applying the test case to the C model of the ASIC.
3 a) HVL: Hardware Verification Language
The testbench required to test the RTL design is coded using HVL. Examples are (VERA, e language and system C).
The complex testbenches like the full chip verification is normally written in HVL.
Prior to the use of HVL, HDLs were used to write the simple testbenches. As the complexity of testbench increases with the increase in the design and functionality HVL are being used to write complex testbenches.
4) Module level Verification:
Each RTL designer codes his module/ modules. He writes a small testbench to test his module so that the bugs caught are fixed at the module level. This verification is called module level verification
5) Chip level Verification
Once all the module are tested separately then One engineer with integrate all the modules into chip level design. This chip level design it tested by instantiated it in the chip level verification environment. This environment can be coded in VERA, E language and /or system C or system verilog.
The verification is an iterative process where the testcases are applied and the response viewed. Incase any bug then the bug is fixed in