High Speed Booth Multiplier

International Journal of Innovations in Engineering and Technology (IJIET)

High Speed Booth Encoded Multiplier By Minimising The Computation Time
S.Arul Mozhi
Assistant Professor, Department of ECE

Aswin Kumar.V, Sundaram.C, Arulmani.S, Balamurugesan.N
Final year, Department of ECE SNS College of Engineering, Coimbatore
Abstract- Two’s complement multipliers are used in most of the applications. The computation time is important in two’s complement multiplier. The computation time gets decreased by reducing the number of gates. The reduction can be achieved by Modified Booth Encoded multiplier Technique. Two’s complement multipliers are used in wide range of applications like multimedia, 3D graphics, signal processing etc. In this project, one row of the partial product array can be reduced without increasing the delay. This MBE technique allows faster computation of the partial product array which is used in most of the multiplier designs.

I. INTRODUCTION Multipliers play an important role in today 's digital signal processing and various other applications. With advances in technology, many researchers have tried and are trying to design multipliers which offer either of the following design targets - high speed, low power consumption, regularity of layout and hence less area or even combination of them in one multiplier thus making them suitable for various high speed, low power and compact VLSI implementation. In parallel multipliers number of partial products to be added is the main parameter that determines the performance of the multiplier. To reduce the number of partial products to be added, Modified Booth algorithm is one of the most popular algorithms. To achieve speed improvements Wallace Tree algorithm can be used to reduce the number of sequential adding stages Booth Multipliers is a powerful algorithm for signed-number multiplication, which treats both positive and negative numbers uniformly. For the standard add-shift operation, each

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