EVEN PARITY BIT GENERATOR
Aim:
The aim of this project is to design a 3-bit even parity generator that can detect a one-bit error in a message and draw the CMOS layout in L-Edit, which can then be simulated using PSPICE.
Abstract:
An even parity bit generator generates an output of 0 if the number of 1’s in the input sequence is even and 1 if the number of 1’s in the input sequence is odd. The checker circuit gives an output of 0 if there is no error in the parity bit generated. Thus it basically checks to see if the parity bit generator is error free or not.
Schematic:
The design procedure is made simple by writing the truth table for the circuit.
Truth table:
Message Even parity bit Checker bit
X Y Z P C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 0
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 0
The circuit can now be derived by drawing the K-map for the output.
From this the minimal output equation is
This function can be implemented using exclusive-or gates. The schematic of the parity generator circuit is shown in Figure 1.
Figure 1: Parity bit generator
Similarly the checker circuit can be designed using XOR gates, where and the circuit is shown in Figure 2.
Figure 2: Checker circuit
Now the parity bit generator and the checker circuit can be combined into one circuit for simplicity. The final schematic of the circuit is shown in Figure 3.
Figure 3: Combined schematic of both parity bit generator and checker circuit
The final layout consists of four XOR gates, which can be
The aim of this project is to design a 3-bit even parity generator that can detect a one-bit error in a message and draw the CMOS layout in L-Edit, which can then be simulated using PSPICE.
Abstract:
An even parity bit generator generates an output of 0 if the number of 1’s in the input sequence is even and 1 if the number of 1’s in the input sequence is odd. The checker circuit gives an output of 0 if there is no error in the parity bit generated. Thus it basically checks to see if the parity bit generator is error free or not.
Schematic:
The design procedure is made simple by writing the truth table for the circuit.
Truth table:
Message Even parity bit Checker bit
X Y Z P C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 0
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 0
The circuit can now be derived by drawing the K-map for the output.
From this the minimal output equation is
This function can be implemented using exclusive-or gates. The schematic of the parity generator circuit is shown in Figure 1.
Figure 1: Parity bit generator
Similarly the checker circuit can be designed using XOR gates, where and the circuit is shown in Figure 2.
Figure 2: Checker circuit
Now the parity bit generator and the checker circuit can be combined into one circuit for simplicity. The final schematic of the circuit is shown in Figure 3.
Figure 3: Combined schematic of both parity bit generator and checker circuit
The final layout consists of four XOR gates, which can be
References: 1. Physical Design of CMOS Integrated circuits using L-Edit by John P.Uyemura. 2.Circuit Design for CMOS VLSI by John P.Uyemura. 3.http://users.ece.gatech.edu/~rdanse/ECE2030/slides/ECE2030_Chapter06_2pp.pdf