EVEN PARITY BIT GENERATOR

Topics: CMOS, MOSFET, Logic gate Pages: 18 (2310 words) Published: November 22, 2014


Aim:
The aim of this project is to design a 3-bit even parity generator that can detect a one-bit error in a message and draw the CMOS layout in L-Edit, which can then be simulated using PSPICE.

Abstract:
An even parity bit generator generates an output of 0 if the number of 1’s in the input sequence is even and 1 if the number of 1’s in the input sequence is odd. The checker circuit gives an output of 0 if there is no error in the parity bit generated. Thus it basically checks to see if the parity bit generator is error free or not.

Schematic:

The design procedure is made simple by writing the truth table for the circuit.

Truth table:
Message Even parity bit Checker bit
X Y Z P C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 0
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 0

The circuit can now be derived by drawing the K-map for the output.

From this the minimal output equation is
This function can be implemented using exclusive-or gates. The schematic of the parity generator circuit is shown in Figure 1.

Figure 1: Parity bit generator

Similarly the checker circuit can be designed using XOR gates, where and the circuit is shown in Figure 2.

Figure 2: Checker circuit

Now the parity bit generator and the checker circuit can be combined into one circuit for simplicity. The final schematic of the circuit is shown in Figure 3.

Figure 3: Combined schematic of both parity bit generator and checker circuit

The final layout consists of four XOR gates, which can be designed, in L-EDIT using the CMOS technology. The basic building blocks in CMOS technology are MOSFET’s. A MOSFET is a metal oxide semiconductor field effect transistor. The advantages of MOSFET over BJT’s are, they are smaller in size and the drain and source terminals are interchangeable. This provides the designers with area minimization on the chip.

Software used:

1. L-EDIT student version for drawing the layouts.
2. PSPICE for simulating the layouts.

Basic building blocks:

MOSFET’s are the basic building blocks. There are three main components to a CMOS transistor. The Source and Drain can be interchanged at the silicon level and occasionally at the device level. These are the main current carrying terminals. The Gate is separated from the Composite (Silicon) by a thin layer of SiO2, which acts as an insulator or dielectric. In the CMOS world you can create a Capacitor by shorting the Source and Drain together calling that one terminal, and using the Gate for the other terminal. The difference between an NMOS and a PMOS device depends on the type of WELL (base) the transistor is sitting in.The layout of a p-channel MOSFET drawn in L-Edit is shown in Figure 4. Layout of a MOSFET using L-Edit is very straightforward. An n-channel device is constructed by creating an n+ region ndiff defined by

ndiff = (ACTIVE) AND (NSELECT)

A POLY over ndiff creates the transistor. The drawing steps for creating the nFET are as follows. 1. Construct an ACTIVE box/polygon.
2. Surround ACTIVE with NSELECT. The intersection of the two is ndiff. 3. Create a POLY box that crosses completely over ndiff and extends beyond the ACTIVE area. This creates the gate.

The actual drawing sequence is not important. However, all design rules should be obeyed. Figure 4 shows the layout of an nMOSFET structure. Each layer is drawn sequentially obeying all the design rules and a DRC is performed to check if there are any...

References: 1. Physical Design of CMOS Integrated circuits using L-Edit by John P.Uyemura.
2.Circuit Design for CMOS VLSI by John P.Uyemura.
3.http://users.ece.gatech.edu/~rdanse/ECE2030/slides/ECE2030_Chapter06_2pp.pdf
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