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4 FPGA-based Embedded Processor
With rising gate densities of FPGA devices, many FPGA vendors now offer a processor that either exists in silicon as a hard IP or can be incorporated within the programmable device as a soft IP. The purpose of having a processor co-exist with conventional digital logic components is to provide flexilibility of combining software and hardware based control in one chip. Many algorithms that are difficult to code in HDL and have update time requirements in milliseconds can use the processor inside the FPGA. A whole suite of tools, consisting of compilers and assemblers help the designer code in C or C++. The motivation of this chapter is to introduce the use of FPGA embedded processors and to integrate custom digitial logic with FPGA-based processors.
4.1 Hardware–Software Task Partitioning
Update time
10–100 ms
Referencing trajectory control
1–10 ms
Control of position and speed loop, sequencing logic
μs
Current and power device PWM control
Fig 4.1. Task update rates
A designer of a digital system identifies tasks and their update time requirements. As shown in Fig. 4.1, a robot controller task pyramid consists of tasks that need microsecond or millisecond update time. In our hypothetical robot control system, the task of robot joint trajectory computation, which needs 10–100 ms update time, is assigned to a processor. The processor is driven by a timer interrupt that updates
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Introduction to Embedded System Design Using Field Programmable Gate Arrays
the trajectory profile every 10–100 ms. The task of motor current and power device PWM control is part of hardware logic (designed using HDL) because it needs to update every 50 μs.
4.2 FPGA Fabric Immersed Processors
The ability to support processor logic has brought a new dimension to the use of FPGA devices. It has provided designers the freedom to partition their designs either for single-threaded software flow or to use concurrent
With rising gate densities of FPGA devices, many FPGA vendors now offer a processor that either exists in silicon as a hard IP or can be incorporated within the programmable device as a soft IP. The purpose of having a processor co-exist with conventional digital logic components is to provide flexilibility of combining software and hardware based control in one chip. Many algorithms that are difficult to code in HDL and have update time requirements in milliseconds can use the processor inside the FPGA. A whole suite of tools, consisting of compilers and assemblers help the designer code in C or C++. The motivation of this chapter is to introduce the use of FPGA embedded processors and to integrate custom digitial logic with FPGA-based processors.
4.1 Hardware–Software Task Partitioning
Update time
10–100 ms
Referencing trajectory control
1–10 ms
Control of position and speed loop, sequencing logic
μs
Current and power device PWM control
Fig 4.1. Task update rates
A designer of a digital system identifies tasks and their update time requirements. As shown in Fig. 4.1, a robot controller task pyramid consists of tasks that need microsecond or millisecond update time. In our hypothetical robot control system, the task of robot joint trajectory computation, which needs 10–100 ms update time, is assigned to a processor. The processor is driven by a timer interrupt that updates
82
Introduction to Embedded System Design Using Field Programmable Gate Arrays
the trajectory profile every 10–100 ms. The task of motor current and power device PWM control is part of hardware logic (designed using HDL) because it needs to update every 50 μs.
4.2 FPGA Fabric Immersed Processors
The ability to support processor logic has brought a new dimension to the use of FPGA devices. It has provided designers the freedom to partition their designs either for single-threaded software flow or to use concurrent
References: 1. 2. 3. 4. 5. Hall TS, Hamblen JO (2004) System-on-a-programmable-chip development platforms in the classroom.IEEE Transactions on Education: 47(4): 502–507 WISHBONE System-on-Chip (SoC) interconnection architecture for portable IP cores. (2002) B.3. http://www.opencores.org/projects.cgi/web/wishbone/wishbone. Accessed 21 May 2008 Klafter RD et al (1989) Robotic engineering, an integrated approach. Prentice-Hall Schilling RJ (1990) Fundamentals of robotics analysis and control. Prentice-Hall, New Jersey Kung Y, Shu G (2005) Development of a FPGA-based motion control IC for robot arm. Paper presented at IEEE ICIT 2005,1397–1402 Further Reading 1. 2. 3. 4. 5. Slater M (1989) Microprocessor–based design, a comprehensive guide to hardware design. Prentice-Hall Mitsubishi Industrial Micro-Robot System Manual for Model RV-M1, MovemasterEx, BFP-A5191E-B Kung Y, Huang P, Chen C (2004) Development of a SOPC for PMSM Drives. Paper presented at the 47th IEEE International Midwest Symposium on Circuits and Systems 2004 Kung Y, Shu G (2005) Development of a FPGA-based motion control IC for robot arm. Paper presented at IEEE ICIT 2005, pp. 1397–1402 Navabi Z (2007) Embedded Core Design with FPGAs. McGraw Hill