# Reversible Logic

**Topics:**Binary-coded decimal, Logic gate, Reversible computing

**Pages:**23 (8994 words)

**Published:**May 5, 2012

Microelectronics Journal 39 (2008) 1693– 1703

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Microelectronics Journal

journal homepage: www.elsevier.com/locate/mejo

Efﬁcient approaches for designing reversible Binary Coded Decimal adders Ashis Kumer Biswas, Md. Mahmudul Hasan, Ahsan Raja Chowdhury, Haﬁz Md. Hasan Babu Ã Department of Computer Science and Engineering, University of Dhaka, Dhaka 1000, Bangladesh

a r t i c l e in fo

Article history: Received 27 November 2007 Received in revised form 5 April 2008 Accepted 16 April 2008 Available online 18 June 2008 Keywords: Reversible logic Garbage output Gate complexity Binary Coded Decimal adder Carry Skip BCD adder Quantum cost

abstract

Reversible logic has become one of the most promising research areas in the past few decades and has found its applications in several technologies; such as low-power CMOS, nanocomputing and optical computing. This paper presents improved and efﬁcient reversible logic implementations for Binary Coded Decimal (BCD) adder as well as Carry Skip BCD adder. It has been shown that the modiﬁed designs outperform the existing ones in terms of number of gates, number of garbage outputs, delay, and quantum cost. In order to show the efﬁciency of the proposed designs, lower bounds of the reversible BCD adders in terms of gates and garbage outputs are proposed as well. & 2008 Elsevier Ltd. All rights reserved.

1. Introduction The advancement in higher-level integration and fabrication process has emerged in better logic circuits and energy loss has also been dramatically reduced over the last decades. This trend of reduction of heat in computation also has its physical limit. According to Landauer [1,2], in logic computation every bit of information loss generates kTln2 joules of heat energy where k is Boltzmann’s constant of 1.38 Â 10À23 J/K and T is the absolute temperature of the environment. At room temperature, the dissipating heat is around 2.9 Â 10À21 J. Energy loss due to Landauer limit is also important as it is likely that the growth of heat generation causing information loss will be noticeable in future. Reversible circuits are fundamentally different from traditional irreversible ones. In reversible logic, no information is lost, i.e. the circuit that does not lose information is reversible. Bennett [3] showed that zero energy dissipation would be possible if the network consists of reversible gates only. Thus, reversibility will be an essential property for the future circuit design. Quantum computation is also gaining popularity as some exponentially hard problems can be solved in polynomial time [4]. We know that quantum computation is reversible. Thus, research in reversible logic is helpful for the development of future technologies; it has the potential to methods of quantum circuit construction resulting in more powerful computers. Quantum technology is not the only one where reversibility is used.

Ã Corresponding author. Tel.: +880 1711 351055; fax: +880 2 8615583.

E-mail address: haﬁzbabu@hotmail.com (H.M. Hasan Babu). 0026-2692/$ - see front matter & 2008 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2008.04.003

Reversible logic has also found its applications in several other disciplines such as nanotechnology [5], DNA technology [6] and optical computing [7]. In computers, numbers are stored in straight binary format. Due to inherent characteristics of ﬂoating-point numbers and limitations on storing formats, not all ﬂoating-point numbers can be represented with desired precision [8]. So, computing in decimal format is gaining popularity as loss due to precision can be avoided in this format. However, hardware support for binary arithmetic allows it to be performed faster than decimal arithmetic. Faster hardware for decimal ﬂoating-point arithmetic is also imminent as it has its importance in ﬁnancial and Internet based applications. So, faster circuits for Binary Coded Decimal...

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Proof. A Carry Skip reversible BCD adder consists of a 4-bit reversible parallel adder, overﬂow detection logic and overﬂow correction logic. A 4-bit parallel adder consists of 4 full adders. According to Lemma 5.2.3, a 4-bit parallel adder can be realized by at least 8 garbage outputs and from Algorithm 5.3.1, it is clear that 4 garbages from the 4 full adders are used to generate the propagate bit P. So, the number of garbage outputs for a reversible 4-bit parallel adder, gcpa reduces to 4. & In the overﬂow detection logic, the overﬂow expression, ¯ F ¼ (T1+T2) T3ÈK is realized where K ¼ PC in È PC 4 . According to Lemma 5.3.2 and Lemma 5.2.2, carry skip logic can be realized by 8 and BCD overﬂow detection logic can be realized by at least zero garbage output. So, the minimum number of garbage outputs for overﬂow detection logic is gcodX8+0 ¼ 8. In the overﬂow correction logic, overﬂow F is propagated. According to our improved design, overﬂow correction logic generates only two garbage outputs. So, the minimum number of garbage outputs for overﬂow correction logic is gcoclX2. As a result, the total number of garbage outputs for a Carry Skip reversible BCD adder is g cBCD Xg cpa þ g cod þ g cocl , where g cpa X4; & Theorem 5.3.2. Let gtcpa be the minimum number of gates for a reversible 4-bit parallel adder, gtcod be the minimum number of gates required by overﬂow detector and gtcocl be the minimum number of gates for overﬂow correction logic. Let gtcBCD be the number of gates for a Carry Skip reversible BCD adder, then gt cBCD Xgt cpa þ gt cod þ gtcocl , where gt cpa X4; gt cod X7 and gtocl X3. Proof. A Carry Skip reversible BCD adder consists of a 4-bit reversible parallel adder, overﬂow detection logic and overﬂow correction logic. A 4-bit parallel adder consists of 4 full adders and according to Lemma 5.1.1, a 4-bit parallel adder can be realized by g cod X8 and g cocl X2.

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A.K. Biswas et al. / Microelectronics Journal 39 (2008) 1693–1703 1703

[17] M.H.A. Khan, M.A. Perkowski, Logic synthesis with cascades of new reversible gate families, in: 6th International Symposium on Representation and Methodology of Future Computing Technology (Reed-Muller), March 2003, pp. 43–55. [18] H. Thapliyal, M.B. Srinivas, A new reversible TSG gate and its application for designing efﬁcient adder circuits, in: 7th International Symposium on Representations and Methodology of Future Computing Technologies, 2005. [19] H. Thapliyal, M.B. Srinivas, Novel reversible TSG gate and its application for designing reversible carry look ahead adder and other adder architectures, in: 10th Asia-Paciﬁc Computer Systems Architecture Conference, 2005. [20] M.H.A. Khan, Design of full-adder with reversible gates, Int. Conf. Comput. Inf. Technol. (2002) 515–519. [21] H. Thapliyal, A.P. Vinod, Designing efﬁcient online testable reversible adders with new reversible gate, IEEE ISCAS (2007) 1085–1088. [22] J. Smoline, D.P. DiVincenzo, Five two-qubit gates are sufﬁcient to implement the quantum Fredkin gate, Phys. Rev. A 53 (4) (1996) 2855–2856. [23] G. Yang, X. Song, W.N.N. Hung, M.A. Perkowski, Bi-direction synthesis for reversible circuits, in: IEEE Computer Society Annual Symposium on VLSI New Frontiers in VLSI Design. [24] W.N.N. Hung, X. Song, G. Yang, J. Yang, M.A. Perkowski, Optimal synthesis of multiple output Boolean functions using a set of quantum gates by symbolic reachability analysis, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 25 (9) (September 2006) 1652–1663. [25] D. Maslov, G.W. Dueck, D.M. Miller, Toffoli network synthesis with templates, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 24 (6) (June 2005) 807–817. [26] Md. Mahmudul Hasan, A.K. Biswas, M. Hasan, A.R. Chowdhury, H.M.H. Babu, A novel approach to design BCD adder and Carry Skip BCD adder, in: 21st International Conference on VLSI Design, 4–8 January 2008, pp. 566–571. [27] Haghparast Majid, Navi Keivan, A novel reversible BCD adder for nanotechnology based systems, Am. J. Appl. Sci. 5 (3) (2008) 282–288 ISSN 1546-9239. Ashis Kumer Biswas has completed his B.Sc. (Honors) in computer science and engineering at University of Dhaka, Bangladesh. He is interested mostly in digital logic synthesis and design, reversible logic circuit design and quantum computations.

Md. Mahmudul Hasan has completed his B.Sc. (Honors) in computer science and engineering from the University of Dhaka, Bangladesh, and he is a student of MS in the same subject. His research interests include logic synthesis and design, reversible logic and fuzzy logic.

Ahsan Raja Chowdhury received his B.Sc. and MS degrees in computer science and engineering from the University of Dhaka, Bangladesh, in 2004 and 2006, respectively. He worked with the Department of Computer Science and Engineering, Northern University, Bangladesh, from 2004 to 2007 as faculty member. Now he is the faculty member of the Department of Computer Science and Engineering, University of Dhaka, Dhaka 1000, Bangladesh. His research interests include logic synthesis and design, reversible logic, image processing, wireless networking. Haﬁz Md. Hasan Babu received his M.Sc. degree in computer science and engineering from the Technical University of Brno, Czech Republic, in 1992 under the Czech Government Scholarship. He obtained his Ph.D. in VLSI CAD in 2000 from the Kyushu Institute of Technology, Japan, under the Japanese Government Scholarship. He worked with the Department of Computer Science and Engineering, Khulna University, Bangladesh, from 1992 to March 2001. Now, he is a professor of the Department of Computer Science and Engineering of University of Dhaka, Dhaka, Bangladesh. He was also the Chairman of this department from February 2003 to February 2006. In 1995, he was at the Asian Institute of Technology (AIT), Thailand, under the DAAD Fellowship from the Federal Republic of Germany. His research interests include logic design and switching theory, representation of logic functions and multiple-valued logic. He is a member of IEEE.

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