Reversible Logic

ARTICLE IN PRESS
Microelectronics Journal 39 (2008) 1693– 1703

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Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo

Efficient approaches for designing reversible Binary Coded Decimal adders
Ashis Kumer Biswas, Md. Mahmudul Hasan, Ahsan Raja Chowdhury, Hafiz Md. Hasan Babu Ã
Department of Computer Science and Engineering, University of Dhaka, Dhaka 1000, Bangladesh

a r t i c l e in fo
Article history: Received 27 November 2007 Received in revised form 5 April 2008 Accepted 16 April 2008 Available online 18 June 2008 Keywords: Reversible logic Garbage output Gate complexity Binary Coded Decimal adder Carry Skip BCD adder Quantum cost

abstract
Reversible logic has become one of the most promising research areas in the past few decades and has found its applications in several technologies; such as low-power CMOS, nanocomputing and optical computing. This paper presents improved and efficient reversible logic implementations for Binary Coded Decimal (BCD) adder as well as Carry Skip BCD adder. It has been shown that the modified designs outperform the existing ones in terms of number of gates, number of garbage outputs, delay, and quantum cost. In order to show the efficiency of the proposed designs, lower bounds of the reversible BCD adders in terms of gates and garbage outputs are proposed as well. & 2008 Elsevier Ltd. All rights reserved.

1. Introduction The advancement in higher-level integration and fabrication process has emerged in better logic circuits and energy loss has also been dramatically reduced over the last decades. This trend of reduction of heat in computation also has its physical limit. According to Landauer [1,2], in logic computation every bit of information loss generates kTln2 joules of heat energy where k is Boltzmann’s constant of 1.38 Â 10À23 J/K and T is the absolute temperature of the environment. At room temperature, the dissipating heat is around 2.9 Â 10À21

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A Carry Skip reversible BCD adder consists of a 4-bit reversible parallel adder, overflow detection logic and overflow correction logic. A 4-bit parallel adder consists of 4 full adders. According to Lemma 5.2.3, a 4-bit parallel adder can be realized by at least 8 garbage outputs and from Algorithm 5.3.1, it is clear that 4 garbages from the 4 full adders are used to generate the propagate bit P. So, the number of garbage outputs for a reversible 4-bit parallel adder, gcpa reduces to 4. & In the overflow detection logic, the overflow expression, ¯ F ¼ (T1+T2) T3ÈK is realized where K ¼ PC in È PC 4 . According to Lemma 5.3.2 and Lemma 5.2.2, carry skip logic can be realized by 8 and BCD overflow detection logic can be realized by at least zero garbage output. So, the minimum number of garbage outputs for overflow detection logic is gcodX8+0 ¼ 8. In the overflow correction logic, overflow F is propagated. According to our improved design, overflow correction logic generates only two garbage outputs. So, the minimum number of garbage outputs for overflow correction logic is gcoclX2. As a result, the total number of garbage outputs for a Carry Skip reversible BCD adder is g cBCD Xg cpa þ g cod þ g cocl , where g cpa X4; & Theorem 5.3.2. Let gtcpa be the minimum number of gates for a reversible 4-bit parallel adder, gtcod be the minimum number of gates required by overflow detector and gtcocl be the minimum number of gates for overflow correction logic. Let gtcBCD be the number of gates for a Carry Skip reversible BCD adder, then gt cBCD Xgt cpa þ gt cod þ gtcocl , where gt cpa X4; gt cod X7 and gtocl X3. Proof. A Carry Skip reversible BCD adder consists of a 4-bit reversible parallel adder, overflow detection logic and overflow correction logic. A 4-bit parallel adder consists of 4 full adders and according to Lemma 5.1.1, a 4-bit parallel adder can be realized by g cod X8 and g cocl X2. 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Babu, A novel approach to design BCD adder and Carry Skip BCD adder, in: 21st International Conference on VLSI Design, 4–8 January 2008, pp. 566–571. [27] Haghparast Majid, Navi Keivan, A novel reversible BCD adder for nanotechnology based systems, Am. J. Appl. Sci. 5 (3) (2008) 282–288 ISSN 1546-9239. Ashis Kumer Biswas has completed his B.Sc. (Honors) in computer science and engineering at University of Dhaka, Bangladesh. He is interested mostly in digital logic synthesis and design, reversible logic circuit design and quantum computations. Md. Mahmudul Hasan has completed his B.Sc. (Honors) in computer science and engineering from the University of Dhaka, Bangladesh, and he is a student of MS in the same subject. His research interests include logic synthesis and design, reversible logic and fuzzy logic. Ahsan Raja Chowdhury received his B.Sc. and MS degrees in computer science and engineering from the University of Dhaka, Bangladesh, in 2004 and 2006, respectively. He worked with the Department of Computer Science and Engineering, Northern University, Bangladesh, from 2004 to 2007 as faculty member. Now he is the faculty member of the Department of Computer Science and Engineering, University of Dhaka, Dhaka 1000, Bangladesh. His research interests include logic synthesis and design, reversible logic, image processing, wireless networking. Hafiz Md. Hasan Babu received his M.Sc. degree in computer science and engineering from the Technical University of Brno, Czech Republic, in 1992 under the Czech Government Scholarship. He obtained his Ph.D. in VLSI CAD in 2000 from the Kyushu Institute of Technology, Japan, under the Japanese Government Scholarship. He worked with the Department of Computer Science and Engineering, Khulna University, Bangladesh, from 1992 to March 2001. Now, he is a professor of the Department of Computer Science and Engineering of University of Dhaka, Dhaka, Bangladesh. He was also the Chairman of this department from February 2003 to February 2006. In 1995, he was at the Asian Institute of Technology (AIT), Thailand, under the DAAD Fellowship from the Federal Republic of Germany. His research interests include logic design and switching theory, representation of logic functions and multiple-valued logic. He is a member of IEEE.