Digital Computer Electronics 3rd Edition Chapters 1 5 Optimized
Digital
Computer
Electronics
Third Edition
Albert Paul Malvino, Ph.D.
Jerald A. Brown
~
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GLENCOE
McGraw-Hill
New York, New York
Columbus, Ohio
Woodland Hills, California
Peoria, Illinois
This textbook was prepared with the assistance of Publishing Advisory Service.
LSI circuit photo: Manfred Kage/Peter Arnold Inc.
To my wife, Joanna, who encourages me to write.
And to my daughters, Joanna, Antonia, Lucinda,
Patricia, and Miriam, who keep me young.
-A.P.M .
. . to my wife Vickie dearest friend fellow adventurer love of my life
-J.A.B.
Library of Congress Cataloging-in-Publication Data
Malvino, Albert Paul.
Digital computerelectronics I Albert Paul Malvino, Jerald A.
Brown. - 3rd ed.
p.
em.
Includes index.
ISBN 0-02-800594-5 (hardcover)
1. Electronic digital computers. 2. Microcomputers. 3. Intel
8085 (Microprocessor) I. Brown, Jerald A. II. Title.
TK7888.3.M337 1993
621.39' 16-dc20
92-5895
CIP
Digital Computer Electronics, Third Edition
Imprint 1999
Copyright© 1993, 1983 by Glencoe/McGraw-Hill. All rights reserved. Copyright© 1983, 1977 by
McGraw-Hill, Inc. All rights reserved. Printed in the United States of America. Except as permitted under the United States Copyright Act, no part of this publication may be reproduced or distributed in any form or by any means, or stored in a database or retrieval system, without prior written permission of the publisher.
ISBN 0-02-800594-5
Printed in the United States of America.
456789101112
004/043
0302010099
Contents
PREFACE
vi
CHAPTER 6. ARITHMETIC-LOGIC UNITS
79
6-1. Binary Addition 6-2. Binary Subtraction
6-3. Half Adders 6-4. Full Adders 6-5. Binary
Adders 6-6. Signed Binary Numbers 6-7. 2's
Complement 6-8. 2's-Complement Adder-Subtracter
PART 1
Digital Principles 1
CHAPTER I. NUMBER SYSTEMS AND
CODES I
1-1. Decimal Odometer
1-2. Binary Odometer
1-3. Number Codes
1-4. Why Binary Numbers Are
Used
1-5. Binary-to-Decimal Conversion
1-6. Microprocessors
1-7. Decimal-to-Binary
Conversion
1-8. Hexadecimal Numbers
1-9. Hexadecimal-Binary Conversions
1-10. Hexadecimal-to-Decimal Conversion
1-11. Decimal-to-Hexadecimal Conversion
1-12. BCD Numbers
1-13. The ASCII Code
CHAPTER 2. GATES
CHAPTER 7. FLIP-FLOPS
90
7-1. RS Latches 7-2. Level Clocking 7-3. D Latches
7-4. Edge-Triggered D Flip-Flops 7-5. Edge-Triggered
JK Flip-Flops
7-6. JK Master-Slave Flip-Flop
CHAPTER 8. REGISTERS AND
COUNTERS I06
8-1.
8-3.
8-5.
8-7.
8-9.
Buffer Registers 8-2. Shift Registers
Controlled Shift Registers 8-4. Ripple Counters
Synchronous Counters 8-6. Ring Counters
Other Counters
8-8. Three-State Registers
Bus-Organized Computers
I9
2-1. Inverters 2-2. OR Gates
2-4. Boolean Algebra
2-3.
AND
Gates
I30
9-1. ROMs
9-2. PROMs and EPROMs 9-3. RAMs
9-4. A Small TTL Memory 9-5. Hexadecimal
Addresses
CHAPTER 3. MORE LOGIC GATES
32
3-1. NOR Gates 3-2. De Morgan's First Theorem
3-3. NAND Gates 3-4. De Morgan's Second Theorem
3-5. EXCLUSIVE-OR Gates 3-6. The Controlled
Inverter 3-7. EXCLUSIVE-NOR Gates
CHAPTER 4. TTL CIRCUITS
CHAPTER 9. MEMORIES
48
PART 2
SAP (Simple-as-Possible)
Computers 140
CHAPTER IO. SAP-I
I40
4-1. Digital Integrated Circuits 4-2. 7400 Devices
4-3. TTL Characteristics 4-4. TTL Overview
4-5. AND-OR-INVERT Gates 4-6. Open-Collector Gates
4-7. Multiplexers
I 0-1 . Architecture
I 0-2. Instruction Set
10-3. Programming SAP-I
10-4. Fetch Cycle
10-5. Execution Cycle
10-6. The SAP-I
Microprogram
I 0-7. The SAP-I Schematic Diagram
10-8. Microprogramming
CHAPTER 5. BOOLEAN ALGEBRA AND
KARNAUGH MAPS 64
CHAPTER II. SAP-2
5-1. Boolean Relations 5-2. Sum-of-Products Method
5-3. Algebraic Simplification 5-4. Karnaugh Maps
5-5. Pairs, Quads, and Octets 5-6. Karnaugh
Simplifications 5-7. Don't-Care Conditions
I73
Il-l. Bidirectional Registers
11-2. Architecture
11-3. Memory-Reference Instructions
11-4. Register
Instructions
11-5. Jump and Call Instructions
11-6. Logic Instructions
11-7. Other Instructions
11-8. SAP-2 Summary
iii
------
CHAPTER 12. SAP-3
CHAPTER 18. ARITHMETIC AND FLAGS
195
12-1. Programming Model
12-2. MOV and MVI
12-3. Arithmetic Instructions
12-4. Increments,
Decrements, and Rotates
12-5. Logic Instructions
12-6. Arithmetic and Logic Immediates
12-7. Jump
Instructions
I2-8. Extended-Register Instructions
12-10. Stack Instructions
12-9. Indirect Instructions
Computer Hardware
Definition of a Microprocessor
Some Common Uses for Microprocessors
Microprocessors Featured in This Text
Access to Microprocessors
CHAPTER 20. SHIFT AND ROT ATE
INSTRUCTIONS 319
CHAPTER 14. PROGRAMMING AND
LANGUAGES 216
Relationship between Electronics and Programming
Programming
14-3. Fundamental Premise
Flowcharts
14-5. Programming Languages
Assembly Language
14-7. Worksheets
CHAPTER 15. SYSTEM OVERVIEW
224
New Concepts
15-1. Computer Architecture
15-2. Microprocessor Architecture
Specific Microprocessor Families
15-4. 6800/6808 Family
15-3. 6502 Family
15-6. 8086/8088 Family
15-5. 8080/8085/Z80 Family
CHAPTER 16. DATA TRANSFER
INSTRUCTIONS 240
New Concepts
16-1. CPU Control Instructions
16-2. Data Transfer Instructions
Specific Microprocessor Families
16-4. 6800/6808 Family
16-3. 6502 Family
16-6. 8086/8088 Family
16-5. 8080/8085/Z80 Family
CHAPTER 17. ADDRESSING MODES-I
263
New Concepts
17-1. What Is an Addressing Mode'?
17-2. The Paging Concept
17-3. Basic Addressing Modes
17-4. 6502 Family
Specific Microprocessor Families
17-6. 8080/8085/Z80 Family
17-5. 6800/6808 Family
17-7. 8086/8088 Family
iv
Contents
New Concepts
18-1. Microprocessors and Numbers
18-2. Arithmetic Instructions
18-3. Flag Instructions
Specific Microprocessor Families
18.4 6502 Family
18-5. 6800/6808 Family
18-6. 8080/8085/Z80 Family
18-7. 8086/8088 Family
New Concepts
19-1 . The AND Instruction
19-2. The OR Instruction
19-3. The EXCLUSIVE-OR (EOR, XOR) Instruction
19-4. The NOT Instruction
19-5. The NEG (NEGate) Instruction
Specific Microprocessor Families
19-6. 6502 Family
19-8. 8080/8085/Z80 Family
19-7. 6800/6808 Family
19-9. 8086/8088 Family
CHAPTER 13. INTRODUCTION TO
MICROPROCESSORS 213
14-1.
14-2.
14-4.
14-6.
270
CHAPTER 19. LOGICAL INSTRUCTIONS
305
PART 3
Programming Popular
Microprocessors 213
13-1 .
13-2.
13-3.
13-4.
13-5.
-··----
New Concepts 20-1. Rotating 20-2. Shifting
20-3. An Example Specific Microprocessor Families
20-4. 6502 Family 20-5. 6800/6808 Family
20-6. 8080/8085/Z80 Family 20-7. 8086/8088 Family
CHAPTER 21. ADDRESSING MODES-II 329
New Concepts 21-1. Advanced Addressing Modes
Specific Microprocessor Families 21-2. 6502 Family
21-3. 6800/6808 Family 21-4. 8080/8085/Z80 Family
21-5. 8086/8088 Family
CHAPTER 22. BRANCHING AND LOOPS 342
New Concepts 22-1. Unconditional Jumps
22-2. Conditional Branching
22-3. Compare and Test Instructions
22-4. Increment and Decrement Instructions
22-5. Nested Loops
Specific Microprocessor Families 22-6. 6502 Family
22-7. 6800/6808 Family 22-8. 8080/8085/Z80 Family
22-9. 8086/8088 Family
CHAPTER 23. SUBROUTINE AND STACK
INSTRUCTIONS 363
New Concepts 23-1. Stack and Stack Pointer
23-2. Branching versus Subroutines
23-3. How Do Subroutines Return?
23-4. Pushing and Popping Registers
Specific Microprocessor Families 23-5. 6502 Family
23-6. 6800/6808 Family 23-7. 8080/8085/Z80 Family
24-8. 8086/8088 Family
PART 4
Microprocessor Instruction
Set Tables 379
A.
Expanded Table of 8085/8080 and Z80 (8080 Subset)
Instructions Listed by Category
381
Mini Table of 8085/8080 and Z80 (8080 Subset)
Instructions Listed by Category
410
Condensed Table of 8085/8080 and Z80 (8080)
Instructions Listed by Category
415
Condensed Table of 8085/8080 and Z80 (8080 Subset)
Instructions Listed by Op Code
417
Condensed Table of 8085/8080 and Z80 (8080 Subset)
Instructions Listed Alphabetically by 8085/8080
Mnemonic
419
Condensed Table of 8085/8080 and Z80 (8080 Subset)
Instructions Listed Alphabetically by Z80 Mnemonic
421
B.
Expanded Table of 6800 Instructions Listed by Category
422
Short Table of 6800 Instructions Listed Alphabetically
434
Short Table of 6800 Instructions Listed by Category
437
c.
Expanded Table of 8086/8088 Instructions Listed by
Category
445
Condensed Table of 8086/8088 Instructions Listed by
Category
465
Condensed Table of 8086/8088 Instructions Listed
Alphabetically
469
D.
Expanded Table of 6502 Instructions Listed by Category
471
Short Table of 6502 Instructions Listed by Category
478
Condensed Table of 6502 Instructions Listed by Category
480
Condensed Table of 6502 Instructions Listed
Alphabetically
481
Condensed Table of 6502 Instructions Listed by Op Code
482
APPENDIXES
485
1. The Analog Interface 2. Binary-HexadecimalDecimal Equivalents 3. 7400 Series TTL
4. Pinouts and Function Tables 5. SAP-I Parts List
6. 8085 Instructions 7. Memory Locations: Powers of 2
8. Memory Locations: 16K and 8K Intervals
9. Memory Locations: 4K Intervals
10. Memory
Locations: 2K Intervals 11. Memory Locations: IK
Intervals
12. Programming Models
Condensed Table of 6800 Instructions Listed by Category
441
Condensed Table of 6800 Instructions Listed
Alphabetically
443
Condensed Table of 6800 Instructions Listed by Op Code
444
ANSWERS TO ODD-NUMBERED PROBLEMS
513
INDEX
519
Contents
V
Preface
Textbooks on microprocessors are sometimes hard to understand. This text attempts to present the various aspects of microprocessors in ways that are understandable and interesting. The only prerequisite to using this textbook is an understanding of diodes and transistors.
A unique aspect of this text is its wide range. Whether you are interested in the student-constructed SAP (simpleas-possible) microprocessor, the 6502, the 6800/6808, the
8080/8085/Z80, or the 8086/8088, this textbook can meet your needs.
The text is divided into four parts. These parts can be used in different ways to meet the needs of a wide variety of students, classrooms, and instructors.
Part I, Digital Principles, is composed of Chapters 1 to
9. Featured topics include number systems, gates, boolean algebra, flip-flops, registers, counters, and memory. This information prepares the student for the microprocessor sections which follow.
Part 2, which consists of Chapters 10 to 12, presents the
SAP (simple-as-possible) microprocessor. The student constructs this processor using digital components. The SAP processor contains the most common microprocessor functions. It features an instruction set which is a subset of that of the Intel 8085-leading naturally to a study of that microprocessor. Part 3, Programming Popular Microprocessors (Chapters
13 to 23), simultaneously treats the MOS/Rockwell 6502, the Motorola 6800/6808, the Intel 8080/8085 and Zilog
Z80, and the 16-bit Intel 8086/8088. Each chapter is divided into two sections. The first section presents new concepts; second section applies the new concepts to each microprocessor family. Discussion, programming examples, and problems are provided. The potential for comparative study is excellent.
This part of the text takes a strong programming approach to the study of microprocessors. Study is centered around the microprocessor's instruction set and programming model.
The 8-bit examples and homework problems can be performed by using either hand assembly or cross-assemblers.
The 16-bit 8086/8088 examples and problems can be performed by using either an assembler or the DOS DEBUG utility. Part 4 is devoted to the presentation of the instruction sets of each microprocessor family in table form. Several tables are provided for each microprocessor family, permitting instructions to be looked up alphabetically, by op code, or by functional category, with varying levels of detail. The same functional categories are correspondingly used in the chapters in Part 3. This coordination between parts makes the learning process easier and more enjoyable.
Additional reference tables are provided in the appendixes. Answers to odd-numbered problems for Chapters 1 to 16 follow the appendixes.
A correlated laboratory manual, Experiments for Digital
Computer Electronics by Michael A. Miller, is available for use with this textbook. It contains experiments for every part of the text. It also includes programming problems for each of the featured microprocessors.
A teacher's manual is available which contains answers to all of the problems and programs for every microprocessor. In addition, a diskette (MS-DOS 360K 5V4-inch diskette) containing cross-assemblers is included in the teacher's manual.
Special thanks to Brian Mackin for being such a patient and supportive editor. To Olive Collen for her editorial work. To Michael Miller for his work on the lab manual.
And to Thomas Anderson of Speech Technologies Inc. for the use of his cross-assemblers. Thanks also to reviewers
Lawrence Fryda, Illinois State University; Malachi McGinnis, ITT Technical Institute, Garland Texas; and Benjamin Suntag.
A man of true science uses but few hard words, and those only when none other will answer his purpose; whereas the smatterer in science thinks that by mouthing hard words he understands hard things.
Herman Melville
vi
Albert Paul Malvino
Jerald A. Brown
PART 1
DIGITAL PRINCIPLES
NUMBER SYSTEMS
AND CODES
Modem computers don't work with decimal numbers.
Instead, they process binary numbers, groups of Os and 1s.
Why binary numbers? Because electronic devices are most reliable when designed for two-state (binary) operation.
This chapter discusses binary numbers and other concepts needed to understand computer operation.
1-1 DECIMAL ODOMETER
The other wheels also reset and carry. After 999 miles the odometer shows
00999
What does the next mile do? The units wheel resets and carries, the tens wheel resets and carries, the hundreds wheel resets and carries, and the thousands wheel advances by 1, to get
01000
Rene Descartes (1596-1650) said that the way to learn a new subject is to go from the known to the unknown, from the simple to the complex. Let's try it.
The Known
Everyone has seen an odometer (miles indicator) in action.
When a car is new, its odometer starts with
00000
After 1 mile the reading becomes
00001
Digits and Strings
The numbers on each odometer wheel are called digits.
The decimal number system uses ten digits, 0 through 9.
In a decimal odometer, each time the units wheel runs out of digits, it resets to 0 and sends a carry to the tens wheel.
When the tens wheel runs out of digits, it resets to 0 and sends a carry to the hundreds wheel. And so on with the remaining wheels.
One more point. A string is a group of characters (either letters or digits) written one after another. For instance,
734 is a string of 7, 3, and 4. Similarly, 2C8A is a string of 2, C, 8, and A.
Successive miles produce 00002, 00003, and so on, up to
00009
A familiar thing happens at the end of the tenth mile.
When the units wheel turns from 9 back to 0, a tab on this wheel forces the tens wheel to advance by I. This is why the numbers change to
00010
1-2 BINARY ODOMETER
Binary means two. The binary number system uses only two digits, 0 and 1. All other digits (2 through 9) are thrown away. In other words, binary numbers are strings of Os and 1s.
Reset-and-Carry
An Unusual Odometer
The units wheel has reset to 0 and sent a carry to the tens wheel. Let's call this familiar action reset-and-carry.
Visualize an odometer whose wheels have only two digits,
0 and 1. When each wheel turns, it displays 0, then I, then
1
---------
back to 0, and the cycle repeats. Because each wheel has only two digits, we call this device a binary odometer.
In a car a binary odometer starts with
0000
(zero)
After I mile, it indicates
0001
(one)
The next mile forces the units wheel to reset and carry; so the numbers change to
0010
(two)
The third mile results in
0011
(three)
What happens after 4 miles? The units wheel resets and carries, the second wheel resets and carries, and the third wheel advances by 1. This gives
0100
(four)
for 3, and so forth. Binary numbers are long when large
amounts are involved. For instance, 101010 represents decimal 42. As another example, 111I 00001111 stands for decimal 3,855.
Computer circuits are like binary odometers; they count and work with binary numbers. Therefore, you have to learn to count with binary numbers, to convert them to decimal numbers, and to do binary arithmetic. Then you will be ready to understand how computers operate.
A final point. When a decimal odometer shows 0036, we can drop the leading Os and read the number as 36.
Similarly, when a binary odometer indicates 0011, we can drop the leading Os and read the number as 11. With the leading Os omitted, the binary numbers are 0, 1, 10, 11,
100, 101, and so on. To avoid confusion with decimal numbers, read the binary numbers like this: zero, one, onezero, one-one, one-zero-zero, one-zero-one, etc.
1-3 NUMBER CODES
People used to count with pebbles. The numbers I, 2, 3 looked like e, ee, eee. Larger numbers were worse: seven appeared as eeeeeee.
Successive miles produce
Codes
0101
0110
0111
(five)
(six)
(seven)
After 8 miles, the units wheel resets and carries, the second wheel resets and carries, the third wheel resets and carries, and the fourth wheel advances by 1. The result is
1000
(eight)
1001
(nine)
The ninth mile gives
From the earliest times, people have been creating codes that allow us to think, calculate, and communicate. The decimal numbers are an example of a code (see Table
1-1). It's an old idea now, but at the time it was as revolutionary; I stands for e, 2 for ee, 3 for eee, and so forth.
Table 1-I also shows the binary code. 1 stands fore, 10 for ee, 11 for eee, and so on. A binary number and a decimal number are equivalent if each represents the same amount of pebbles. Binary 10 and decimal 2 are equivalent because each represents ee. Binary I01 and decimalS are equivalent because each stands for eeeee.
and the tenth mile produces
TABLE 1-1. NUMBER CODES
1010
(ten)
Decimal
(Try working out a few more readings on your own.)
You should have the idea by now. Each mile advances the units wheel by 1. Whenever the units wheel runs out of digits, it resets and carries. Whenever the second wheel runs out of digits, it resets and carries. And so for the other wheels. Binary Numbers
A binary odometer displays binary numbers, strings of Os and Is. The number 000 I stands for I , 00 I 0 for 2, 00 II
2
Digital Computer Electronics
0
1
2
3
4
5
6
7
8
9
Pebbles
Binary
None
•
••
•••
••••
•
••••
••••••
•••••••
••••••••
•••••••••
0
I
10
II
100
101
110
111
1000
1001
Equivalence is the common ground between us and computers; it tells us when we're talking about the same thing. If a computer comes up with a binary answer of I 0 I, equivalence means that the decimal answer is 5. As a start to understanding computers, memorize the binary-decimal equivalences of Table 1-1.
EXAMPLE
TABLE 1-2. BINARY-TO-DECIMAL
EQUIVALENCES
1-1
Figure l-1a shows four light-emitting diodes (LEDs). A dark circle means that the LED is off; a light circle means it's on. To read the display, use this code:
Decimal
Binary
Decimal
Binary
0
1
2
3
4
5
6
7
0000
0001
0010
0011
0100
0101
0110
0111
8
9
10
11
12
13
14
15
1000
1001
1010 lOll 1100
1101
1110
1111
eo eo
(b)
(a)
Therefore, you should memorize the equivalences of Table
1-2.
Fig. 1-1 LED display of binary numbers.
LED
Binary
Off
0
1-4 WHY BINARY NUMBERS
ARE USED
On
The word "computer" is misleading because it suggests a machine that can solve only numerical problems. But a computer is more than an automatic adding machine. It can play games, translate languages, draw pictures, and so on.
To suggest this broad range of application, a computer is often referred to as a data processor.
What binary number does Fig. 1-1a indicate? Fig. 1-1b?
SOLUTION
Program and Data
Figure 1-1a shows off-off-on-on. This stands for binary
0011 , equivalent to decimal 3.
Figure 1-lb is off-on-off-on, decoded as binary 0101 and equivalent to decimal 5.
EXAMPLE
Data means names, numbers, facts, anything needed to work out a problem. Data goes into a computer, where it is processed or manipulated to get new information. Before it goes into a computer, however, the data must be coded in binary form. The reason was given earlier: a computer's circuits can respond only to binary numbers.
Besides the data, someone has to work out a program, a list of instructions telling the computer what to do. These instructions spell out each and every step in the data processing. Like the data, the program must be coded in binary form before it goes into the computer.
So the two things we must input to a computer are the program and the data. These are stored inside the computer before the processing begins. Once the computer run starts, each instruction is executed and the data is processed.
1-2
A binary odometer has four wheels. What are the successive binary numbers?
SOLUTION
As previously discussed, the first eight binary numbers are
0000, 0001, 0010, 0011, 0100, 0101, 0110, and 0111. On the next count, the three wheels on the right reset and carry; the fourth wheel advances by one. So the next eight numbers are 1000, 1001, 1010, lOll, 1100, 1101, 1110, and 1111.
The final reading of 1111 is equivalent to decimal 15. The next mile resets all wheels to 0, and the cycle repeats.
Being able to count in binary from 0000 to 1111 is essential for understanding the operation of computers.
Hardware and Software
The electronic, magnetic, and mechanical devices of a computer are known as hardware. Programs are called software. Without software, a computer is a pile of ''dumb'' metal. Chapter 1
--------------
~·~
·-----
Number Systems and Codes
3
------~---
Another Code
An analogy may help. A phonograph is like hardware and records are like software. The phonograph is useless without records. Furthermore, the music you get depends on the record you play. A similar idea applies to computers.
A computer is the hardware and programs are the software.
The computer is useless without programs. The program stored in the computer determines what the computer will do; change the program and the computer processes the data in a different way.
Two-state operation is universal in digital electronics. By deliberate design, all input and output voltages are either low or high. Here's how binary numbers come in: low voltage represents binary 0, and high voltage stands for binary 1. In other words, we use this code:
Voltage
Binary
0
Low
High
Transistors
Computers use integrated circuits (ICs) with thousands of transistors, either bipolar or MOS. The parameters (~do fc 0 , gm, etc.) can vary more than 50 percent with temperature change and from one transistor to the next. Yet these computer ICs work remarkably well despite the transistor variations. How is it possible?
The answer is two-state design, using only two points on the load line of each transistor. For instance, the common two-state design is the cutoff-saturation approach; each transistor is forced to operate at either cutoff or saturation.
When a transistor is cut off or saturated, parameter variations have almost no effect. Because of this, it's possible to design reliable two-state circuits that are almost independent of temperature change and transistor variations.
For instance, the base voltages of Fig. 1-2 are low-lowhigh-high, or binary 0011. The collector voltages are highhigh-low-low, or binary 1100. By changing the base voltages we can store any binary number from 0000 to 1111 (decimal
0 to 15).
Bit
Bit is an abbreviation for binary digit. A binary number like 1100 has 4 bits; 110011 has 6 bits; and 11001100 has
8 bits. Figure 1-2 is a 4-bit register. To store larger binary numbers, it needs more transistors. Add two transistors and you get a 6-bit register. With four more transistors, you'd have an 8-bit register.
Transistor Register
Nonsaturated Circuits
Here's an example of two-state design. Figure 1-2 shows a transistor register. (A register is a string of devices that store data.) The transistors on the left are cut off because the input base voltages are 0 V. The dark shading symbolizes the cutoff condition. The two transistors on the right have base drives of 5 V.
The transistors operate at either saturation or cutoff. A base voltage of 0 V forces each transistor to cut off, while a base voltage of 5 V drives it into saturation. Because of this two-state action, each transistor stays in a given state until the base voltage switches it to the opposite state.
Don't get the idea that all two-state circuits switch between cutoff and saturation. When a bipolar transistor is heavily saturated, extra carriers are stored in the base region. If the base voltage suddenly switches from high to low, the transistor cannot come out of saturation until these extra carriers have a chance to leave the base region. The time it takes for these carriers to leave is called the saturation delay time td. Typically, td is in nanoseconds.
In most applications the saturation delay time is too short to matter. But some applications require the fastest possible
,-------------~~-------------.--------------~--o+5V
1 kD.
+5
v
ov
ov
(Approx.)
(Approx.)
10 k!l
ov
Fig. 1-2 Transistor register.
4
Digital Computer Electronics
ov
+5 v
+5 v
switching time. To get this maximum speed, designers have come up with circuits that switch from cutoff (or near cutoff) to a higher point on the load line (but short of saturation). These nonsaturated circuits rely on clamping diodes or heavy negative feedback to overcome transistor variations. Remember this: whether saturated or nonsaturated circuits are used, the transistors switch between distinct points on the load line. This means that all input and output voltages are easily recognized as low or high, binary 0 or binary l.
/
(a)
{b)
Fig. 1-3 Core register.
Magnetic Cores
Early digital computers used magnetic cores to store data.
Figure 1-3a shows a 4-bit core register. With the righthand rule, you can see that conventional current into a wire produces a clockwise flux; reversing the current gives a counterclockwise flux. (The same result is obtained if electron-flow is assumed and the left-hand rule is used.)
The cores have rectangular hysteresis loops; this means that flux remains in a core even though the magnetizing current is removed (see Fig. l-3b). This is why a core register can store binary data indefinitely. For instance, let's use the following code:
Flux
Binary
Counterclockwise
Clockwise
0
Then, the core register of Fig. 1-3b stores binary 1001, equivalent to decimal 9. By changing the magnetizing currents in Fig. 1-3a we can change the stored data.
To store larger binary numbers, add more cores. Two cores added to Fig. 1-3a result in a 6-bit register; four more cores give an 8-bit register.
The memory is one of the main parts of a computer.
Some memories contain thousands of core registers. These registers store the program and data needed to run the computer. Other Two-State Examples
The simplest example of a two-state device is the on-off switch. When this switch is closed, it represents binary 1; when it's open, it stands for binary 0.
Punched cards are another example of the two-state concept. A hole in a card stands for binary 1 , the absence of a hole for binary 0. Using a prearranged code, a cardpunch machine with a keyboard can produce a stack of cards containing the program and data needed to run a computer. Magnetic tape can also store binary numbers. Tape recorders magnetize some points on the tape (binary 1), while leaving other points unmagnetized (binary 0). By a prearranged code, a row of points represents either a coded instruction or data. In this way, a reel of tape can store thousands of binary instructions and data for later use in a computer. Even the lights on the control panel of a large computer are binary; a light that's on stands for binary 1, and one that's off stands for binary 0. In a 16-bit computer, for instance, a row of 16 lights allows the operator to see the binary contents in different computer registers. The operator can then monitor the overall operation and, when necessary, troubleshoot. In summary, switches, transistors, cores, cards, tape, lights, and almost all other devices used with computers are based on two-state operation. This is why we are forced to use binary numbers when analyzing computer action.
EXAMPLE
1-3
Figure 1-4 shows a strip of magnetic tape. The black circles are magnetized points and the white circles unmagnetized points. What binary number does each horizontal row represent? ooooe••• eooooeeo •o••o••• ooeeoooe •••ooeeo oeooeooe eeooeeoe
Fig. 1-4 Binary numbers on magnetic tape.
SOLUTION
The tape stores these binary numbers:
Row
Row
Row
Row
1
2
3
4
00001111
10000110
10110111
00110001
Chapter 1
Row 5
Row 6
Row 7
11100110
01001001
11001101
Number Systems and Codes
5
------------------~·----
(Note: these binary numbers may represent either coded instructions or data.)
A string of 8 bits is called a byte. In this example, the magnetic tape stores 7 bytes. The first byte (row 1) is
00001111 . The second byte (row 2) is 10000110. The third byte is 10110111. And so on.
A byte is the basic unit of data in computers. Most computers process data in strings of 8 bits or some multiple
(16, 24, 32, and so on). Likewise, the memory stores data in strings of 8 bits or some multiple of 8 bits.
(1 X 24 )
+
- - -
(1 X 23 ) + (0 X 22 ) + (0 X 2 1)
+ (1 X 2°) = 16 + 8 + 0 + 0 +
25
Binary 11001 is therefore equivalent to decimal 25.
As another example, the byte 11001100 converts to decimal as follows:
(1 X 26 ) + (0 X 25 ) + (0 X 24 )
(1 X 23 ) + (1 X 22) + (0 X 2 1) + (0 X 2°)
(1 X 27)
+
+
= 128 + 64 + 0 + 0 + 8 + 4 + 0 + 0 = 204
So, binary 11001100 is equivalent to decimal 204.
1-5 BINARY-TO-DECIMAL
CONVERSION
Fast and Easy Conversion
You already know how to count to 15 using binary numbers.
The next thing to learn is how to convert larger binary numbers to their decimal equivalents.
I I I I I I I
0
5
10
4
103
102
3
10
4
1
10°
24
23
0
0
22
21
20
(b)
(a)
Here's a streamlined way to convert a binary number to its decimal equivalent:
1.
2.
3.
4.
Fig. 1-5 (a) Decimal weights; (b) binary weights.
For instance, binary 1101 converts to decimal as follows:
2.
The decimal number system is an example of positional notation; each digit position has a weight or value. With decimal numbers the weights are units, tens, hundreds, thousands, and so on. The sum of all digits multiplied by their weights gives the total amount being represented.
For instance, Fig. l-5a illustrates a decimal odometer.
Below each digit is its weight. The digit on the right has a weight of 10° (units), the second digit has a weight of 10 1
(tens), the third digit a weight of 10 2 (hundreds), and so forth. The sum of all units multiplied by their weights is
X
104 )
+ (7
+ (4
X
X
0
1.
Decimal Weights
(5
Write the binary number.
Write the weights 1, 2, 4, 8,
. , under the binary digits. Cross out any weight under a 0.
Add the remaining weights.
103 ) + (0 X 102 ) + (3 X 10 1)
10°) = 50,000 + 7000 + 0 + 30
= 57,034
+4
8
3. 8
4.
8
4
2
4
0
+4 +0 + 1
=
(Write binary number)
(Write weights)
(Cross out weights)
(Add weights)
13
You can compress the steps even further:
1
(Step 1)
(Steps 2 to 4)
1 0
8 4
~
1~13
As another example, here's the conversion of binary
Ill 0101 in compressed form:
1
1
64
32
1
16
0
1 0
~
4
~
Base or Radix
Binary Weights
Positional notation is also used with binary numbers because each digit position has a weight. Since only two digits are used, the weights are powers of 2 instead of 10. As shown in the binary odometer of Fig. l-5b, these weights are 2°
(units), 2 1 (twos), 22 (fours), 23 (eights), and 24 (sixteens).
If longer binary numbers are involved, the weights continue in ascending powers of 2.
The decimal equivalent of a binary number equals the sum of all binary digits multiplied by their weights. For instance, the binary reading of Fig. l-5b has a decimal equivalent of
6
Digital Computer Electronics
The base or radix of a number system equals the number of digits it has. Decimal numbers have a base of 10 because digits 0 through 9 are used. Binary numbers have a base of 2 because only the digits 0 and 1 are used. (In terms of an odometer, the base or radix is the number of digits on each wheel.)
A subscript attached to a number indicates the base of the number. 100 2 means binary 100. On the other hand,
100 10 stands for decimal 100. Subscripts help clarify equations where binary and decimal numbers are mixed. For instance, the last two examples of binary-to-decimal conversion can be written like this:
11012 = 1310
11101012 = 11710
Microcomputer
What is inside a computer? What is a microprocessor? What is a microcomputer?
As the name implies, a microcomputer is a small computer.
More specifically, a microcomputer is a computer that uses a microprocessor for its CPU. The typical microcomputer has three kinds of chips: microprocessor (usually one chip), memory (several chips), and l/0 (one or more chips).
If a small memory is acceptable, a manufacturer can fabricate all computer circuits on a single chip. For instance, the 8048 from Intel Corporation is a one-chip microcomputer with an 8-bit CPU, 1,088 bytes of memory, and 27 l/0 lines. Computer
Powers of 2
The five main sections of a computer are input, memory, arithmetic and logic, control, and output. Here is a brief description of each.
Input This consists of all the circuits needed to get programs and data into the computer. In some computers the input section includes a typewriter keyboard that converts letters and numbers into strings of binary data.
Memory This stores the program and data before the computer run begins. It also can store partial solutions during a computer run, similar to the way we use a scratchpad while working out a problem.
Control This is the computer's center of gravity, analogous to the conscious part of the mind. The control section directs the operation of all other sections. Like the conductor of an orchestra, it tells the other sections what to do and when to do it.
Arithmetic and logic This is the number-crunching section of the machine. It can also make logical decisions.
With control telling it what to do and with memory feeding it data, the arithmetic-logic unit (ALU) grinds out answers to number and logic problems.
Output This passes answers and other processed data to the outside world. The output section usually includes a video display to allow the user to see the processed data.
Microprocessor design started with 4-bit devices, then evolved to 8- and 16-bit devices. In our later discussions of microprocessors, powers of 2 keep coming up because of the binary nature of computers. For this reason, you should study Table 1-3. It lists the powers of 2 encountered in microcomputer analysis. As shown, the abbreviation K stands for 1,024 (approximately 1,000). t Therefore, 1K means I ,024, 2K stands for 2,048, 4K for 4,096, and so on. Most personal microcomputers have 640K (or greater) memories that can store 655,360 bytes (or more).
In this book we will use subscripts when necessary for clarity. 1-6 MICROPROCESSORS
Microprocessor
The control section and the ALU are often combined physically into a single unit called the central processing unit (CPU). Furthermore, it's convenient to combine the input and output sections into a single unit called the inputoutput (110) unit. In earlier computers, the CPU, memory, and 1/0 unit filled an entire room.
With the advent of integrated circuits, the CPU, memory, and 1/0 unit have shrunk dramatically. Nowadays the CPU can be fabricated on a single semiconductor chip called a microprocessor. In other words, a microprocessor is nothing more than a CPU on a chip.
Likewise, the l/0 circuits and memory can be fabricated on chips. In this way, the computer circuits that once filled a room now fit on a few chips.
TABLE 1-3. POWERS OF 2
Powers of 2
Decimal equivalent
Abbreviation
20
2'
22
23
24
25
26
27
28
29
210
2"
212
213
2'4
2'5
2'6
2
4
8
16
32
64
128
256
512
1,024
2,048
4,096
8,192
16,384
32,768
65,536
1K
2K
4K
8K
16K
32K
64K
t The abbreviations lK, 2K, and so on, became established before K- for kilo- was in common use. Retaining the capital K serves as a useful reminder that K only approximates 1,000.
Chapter 1
Number Systems and Codes
7
1-7 DECIMAL-TO-BINARY
CONVERSION
Next, you need to know how to convert from decimal to binary. After you know how it's done, you will be able to understand how circuits can be built to convert decimal numbers into binary numbers.
Double-Dabble
Double-dabble is a way of converting any decimal number to its binary equivalent. It requires successive division by
2, writing down each quotient and its remainder. The remainders are the binary equivalent of the decimal number.
The only way to understand the method is to go through an example, step by step.
Here is how to convert decimal13 to its binary equivalent.
Step 1. Divide 13 by 2, writing your work like this:
In this final division, 2 does not divide into 1; therefore,
the quotient is 0 with a remainder of 1.
Whenever you arrive at a quotient of 0 with a remainder of 1, the conversion is finished. The remainders when read downward give the binary equivalent. In this example, binary 1101 is equivalent to decimal 13.
Double-dabble works with any decimal number. Progressively divide by 2, writing each quotient and its remainder. When you reach a quotient of 0 and a remainder of 1, you are finished; the remainders read downward are the binary equivalent of the decimal number.
Streamlined Double-Dabble
There's no need to keep writing down 2 before each division because you're always dividing by 2. From now on, here's how to show the conversion of decimal 13 to its binary equivalent: 1 ~ (first remainder)
6
The quotient is 6 with a remainder of 1.
Step 2. Divide 6 by 2 to get
3
0
~
(second remainder)
EXAMPLE
1-4
Convert decimal 23 to binary.
This division gives 3 with a remainder of 0.
Step 3. Again you divide by 2:
1 ~ (third remainder)
SOLUTION
The first step in the conversion looks like this:
11
2) 23
After all divisions, the finished work looks like this:
Here you get a quotient of I and a remainder of 1.
Step 4. One more division by 2 gives
0
Read down This says that binary 10111 is equivalent to decimal 23.
8
Digital Computer Electronics
1-8 HEXADECIMAL NUMBERS
Hexadecimal numbers are extensively used in microprocessor work. To begin with, they are much shorter than binary numbers. This makes them easy to write and remember. Furthermore, you can mentally convert them to binary form whenever necessary.
An Unusual Odometer
Hexadecimal means 16. The hexadecimal number system has a base or radix of 16. This means that it uses 16 digits to represent all numbers. The digits are 0 through 9, and
A through F as follows: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B,
C, D, E, and F. Hexadecimal numbers are strings of these digits like 8A5, 4CF7, and EC58.
An easy way to understand hexadecimal numbers is to visualize a hexadecimal odometer. Each wheel has 16 digits on its circumference. As it turns, it displays 0 through 9 as before. But then, instead of resetting, it goes on to display A, B, C, D, E, and F.
The idea of reset and carry applies to a hexadecimal odometer. When a wheel turns from F back to 0, it forces the next higher wheel to advance by 1. In other words, when a wheel runs out of hexadecimal digits, it resets and carries. If used in a car, a hexadecimal odometer would count as follows. When the car is new, the odometer shows all
Os:
0000
(zero)
The next 15 miles produce these readings: 0011, 0012,
0013, 0014, 0015, 0016, 0017, 0018, 0019, 001A, OOlB,
OOlC, OOlD, 001E, and OOlF. Once again, the least significant wheel has run out of digits. So, the next mile results in a reset-and-carry:
0020
(thirty-two)
Subsequent readings are 0021, 0022, 0023, 0024, 0025,
0026,0027,0028,0029, 002A, 002B, 002C, 002D, 002E, and 002F.
You should have the idea by now. Each mile advances the least significant wheel by 1. When this wheel runs out of hexadecimal digits, it resets and carries. And so on for the other wheels. For instance, if the odometer reading is
835F
the next reading is 8360. As another example, given
5FFF
the next hexadecimal number is 6000.
Equivalences
Table 1-4 shows the equivalences between hexadecimal, binary, and decimal digits. Memorize this table. It's essential that you be able to convert instantly from one system to another. The next 9 miles produce readings of
0001
0002
0003
0004
0005
0006
0007
0008
0009
(one)
(two)
(three)
(four)
(five)
(six)
(seven)
(eight)
(nine)
The next 6 miles give
OOOA
OOOB
OOOC
OOOD
OOOE
OOOF
(ten)
(eleven)
(twelve)
(thirteen)
(fourteen)
(fifteen)
At this point the least significant wheel has run out of digits. Therefore, the next mile forces a reset-and-carry to get 0010
(sixteen)
TABLE 1-4. EQUIVALENCES
Hexadecimal
Binary
Decimal
0
1
2
3
4
5
6
7
8
9
A
B
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
c
D
E
F
Chapter 1
Number Systems and Codes
9
1-9 HEXADECIMAL-BINARY
CONVERSIONS
EXAMPLE 1-5
Solve the following equation for x:
After you know the equivalences of Table 1-4, you can mentally convert any hexadecimal string to its binary equivalent and vice versa.
SOLUTION
Hexadecimal to Binary
To convert a hexadecimal number to a binary number, convert each hexadecimal digit to its 4-bit equivalent, using
Table 1-4. For instance, here's how 9AF converts to binary:
9
~
1001
A
~
1010
F
~
1111
As another example, C5E2 converts like this:
c
5
~
0101
~
1100
E
~
1110
2
~
0010
Incidentally, for easy reading it's common practice to leave a space between the 4-bit strings. For example, instead of writing C5E2 16
=
x 16 = 1111111111111111 2
This is the same as asking for the hexadecimal equivalent of binary 1111 1111 1111 1111. Since hexadecimal F is equivalent to 1111, x = FFFF. Therefore,
FFFF 16
EXAMPLE
=
1-6
As mentioned earlier, the memory contains thousands of registers (core or semiconductor) that store the program and data needed for a computer run. These memory registers are known as memory locations. A typical microcomputer may have up to 65,536 memory locations, each storing 1 byte. Suppose the first 16 memory locations contain these bytes: 0011
1100
0101
0010
1111
0010
1101
0100
0111
1100
1000
0010
0010
0011
0011
0001
1100010111100010 2
we can write
C5E2 16
=
1100 0101 1110 0010 2
Binary to Hexadecimal
To convert in the opposite direction, from binary to hexadecimal, you again use Table 1-4. Here are two examples. The byte 1000 1100 converts as follows:
1000
~
8
1100
~
1111 1111 1111 1111 2
1100
1101
0111
1000
0001
1010
0100
0000
0111
0011
0100
1000
0001
1010
1110
1111
Convert these bytes to their hexadecimal equivalents.
c
SOLUTION
The 16-bit number 1110 1000 1101 0110 converts like this:
Here are the stored bytes and their hexadecimal equivalents:
1110
~
E
1000
~
8
1101
~
D
0110
~
6
In both these conversions, we start with a binary number and wind up with the equivalent hexadecimal number.
I 0
Digital Computer Electronics
Memory Contents
0011 1100
11001101
0101 0111
0010 1000
1111 0001
Hex Equivalents
3C
CD
57
28
F1
0010 1010
1101 0100
0100 0000
0111 0111
11000011
1000 0100
0010 1000
0010 0001
0011 1010
0011 1110
0001 1111
2A
D4
40
1100
0001
0101
0100
0010
1111
77
C3
84
28
21
3A
3E
lF
What's the point of this example? When talking about the contents of a computer memory, we can use either binary numbers or hexadecimal numbers. For instance, we can say that the first memory location contains 0011 1100, or we can say that it contains 3C. Either string gives the same information. But notice how much easier it is to say, write, and think 3C than it is to say, write, and think 0011
1100. In other words, hexadecimal strings are much easier for people to work with. This is why everybody working with microprocessors uses hexadecimal notation to represent particular bytes.
What we have just done is known as chunking, replacing longer strings of data with shorter ones. At the first memory location we chunk the digits 0011 1100 into 3C. At the second memory location we chunk the digits 1100 1101 into CD, and so on.
0011
1001
1010
1101
1100
1000
The first memory location stores the byte 1010 0 Ill, the second memory location stores the byte 0010 1000, and so on. This example emphasizes a widespread industrial practice. Microcomputers are programmed to display chunked data, often hexadecimal. The user is expected to know hexadecimal-binary conversions. In other words, a computer manufacturer assumes that you know that A7 represents
10 10 0111 , 28 stands for 00 10 1000, and so on.
One more point. Notice that each memory location in this example stores 1 byte. This is typical of first-generation microcomputers because they use 8-bit microprocessors.
1-10 HEXADECIMAL-TO-DECIMAL
CONVERSION
You often need to convert a hexadecimal number to its decimal equivalent. This section discusses methods for doing it.
Hexadecimal to Binary to Decimal
EXAMPLE
1-7
The typical microcomputer has a typewriter keyboard that allows you to enter programs and data; a video screen displays answers and other information.
Suppose the video screen of a microcomputer displays the hexadecimal contents of the first eight memory locations as One way to convert from hexadecimal to decimal is the two-step method of converting from hexadecimal to binary and then from binary to decimal. For instance, here's how to convert hexadecimal 3C to its decimal equivalent.
Step 1. Convert 3C to its binary equivalent:
A7
28
C3
c
3
t
t
0011
1100
Step 2. Convert 0011 1100 to its decimal equivalent:
19
SA
4D
2C
F8
0
0
J.28' M
1
32
16
1 1 0
8 4 ~
0
~
-7
60
Therefore, decimal 60 is equivalent to hexadecimal 3C. As an equation,
What are the binary contents of the memory locations?
SOLUTION
Positional-Notation Method
Convert from hexadecimal to binary to get
10100111
0010 1000
Positional notation is also used with hexadecimal numbers because each digit position has a weight. Since 16 digits are used, the weights are the powers of 16. As shown in
Chapter 1
Number Systems and Codes
11
---
------------------
I I I I I
F
1Eil
8
162
6
E
161
1~
Fig. 1-6 Hexadecimal weights.
the hexadecimal odometer of Fig. 1-6, the weights are 16°,
161, 162 , and 16 3 . If longer hexadecimal numbers are involved, the weights continue in ascending powers of 16.
The decimal equivalent of a hexadecimal string equals the sum of all hexadecimal digits multiplied by their weights.
(In processing hexadecimal digits A through F, use 10 through 15.) For instance, the hexadecimal reading of Fig.
1-6 has a decimal equivalent of
(F
16 3 ) + (8 X 162 ) + (E X 16 1) + (6
= (15 X 16 3) + (8 X 162 ) + (14 X 16 1)
= 61,440 + 2,048 + 224 + 6
= 63,718
X
+
16°)
(6 X 16°)
3C
CD
0002
57
0003
28
A 64K memory has 65,536 hexadecimal addresses from
0000 to FFFF. The equivalent binary addresses are from
to
1111 1111 1111 1111
The first 8 bits are called the upper byte (VB); the second
8 bits are the lower byte (LB). If you have to do a lot of binary-hexadecimal-decimal conversions, use the table of equivalents in Appendix 2, which shows all the values for a 64 K memory.
Appendix 2 has four headings: binary, hexadecimal, UB decimal, and LB decimal. Given a 16-bit address, you convert the upper byte to its decimal equivalent (UB decimal), the lower byte to its decimal equivalent (LB decimal), and then add the two decimal equivalents. For instance, suppose you want to convert
63,71810
0001
Table of Binary-Hexadecimal-Decimal
Equivalents
0000 0000 0000 0000
X
In other words,
0000
the people living in the house. Figure 1-7a emphasizes the point. At address 0000 the stored contents are 3C (equivalent to 0011 1100). At address 0001 the stored contents are CD, at address 0002 the stored contents are 57, and so on.
Figure 1-7b shows how to visualize a 64K memory. The first address is 0000, and the last is FFFF.
0000
0004
F1
0005
0006
2A
04
0007
40
16
65,536
0008
77
locations
locations
0009
C3
OOOA
84
0008
28
oooc
21
0000
3A
OOOE
3E
OOOF
1F
1101 0111 1010 0010 to its decimal equivalent. The upper byte is 1101 0111, or hexadecimal D7; the lower byte is 1010 0010, or A2. Using
Appendix 2, find D7 and its UB decimal equivalent
D7
55,040
Next, find A2 and its LB decimal equivalent
FFFF
(a)
A2
162
Add the UB and LB decimal equivalents to get
55,040
Memory Locations and Addresses
If a certain microcomputer has 64K memory, meaning
65,536 memory locations, each is able to store 1 byte. The different memory locations are identified by hexadecimal numbers called addresses. For instance, Fig. l-7a shows the first 16 memory locations; their addresses are from 0000 to OOOF.
The address of a memory location is different from its stored contents, just as a house address is different from
Digital Computer Electronics
~
(b)
Fig. 1-7 (a) First 16 words in memory; (b) 64K memory.
12
~
+ 162
=
55,202
This is the decimal equivalent of hexadecimal D7 A2 or binary 1101 0111 1010 0010.
Once familiar with Appendix 2, you will find it enormously helpful. It is faster, more accurate, and less tiring than other methods. The only calculation required is adding the UB and LB decimal, easily done mentally, with pencil and paper, or if necessary, on a calculator. Furthermore, if you are interested in converting only the lower byte, no calculation is required, as shown in the next example.
EXAMPLE
1-8
EXAMPLE
1-9
Convert hexadecimal 7E to its decimal equivalent.
Convert decimal 141 to hexadecimal.
SOLUTION
SOLUTION
When converting only a single byte, all you are dealing with is the lower byte. With Appendix 2, look up 7E and its LB decimal equivalent to get
Whenever the decimal number is between 0 and 255, all you have to do is look up the decimal number and its hexadecimal equivalent. With Appendix 2, you can see at a glance that
7E
~
126
8D
In other words, Appendix 2 can be used to convert single bytes to their decimal equivalents (LB decimal) or double bytes to their decimal equivalents (UB decimal + LB decimal). 1-11 DECIMAL-TO-HEXADECIMAL
CONVERSION
One way to perform decimal-to-hexadecimal conversion is to go from decimal to binary then to hexadecimal. Another way is hex-dabble. The idea is to divide successively by
16, writing down the remainders. (Hex -dabble is like doubledabble except that 16 is used for the divisor instead of 2.)
Here's an example of how to convert decimal 2,479 into hexadecimal form. The first division is
154
15
EXAMPLE
141
1-10
Convert decimal 36,020 to its hexadecimal equivalent.
SOLUTION
If the decimal number is between 256 and 65,535, you need to proceed as follows. First, locate the largest UB decimal that is less than 36,020. In Appendix 2, the largest
UB decimal is
UB decimal
=
35,840
which has a hexadecimal equivalent of
F
8C
16 ) 2,479
~
~
35,840
This is the upper byte.
Next, subtract the UB decimal from the original decimal number: The next step is
9
10
A
15
F
36,020 - 35,840 = 180
The difference 180 has a hexadecimal equivalent
B4
The final step is
Read
down
0
9 9
)9
10
A
) 154
15
F
~
180
This is the lower byte.
By combining the upper and lower bytes, we get the complete answer: 8CB4. This is the hexadecimal equivalent of 36,020.
After a little practice, you will find Appendix 2 to be one of the fastest methods of decimal-hexadecimal conversion.
16 ) 2,479
Notice how similar hex-dabble is to double-dabble. Also, remainders greater than 9 have to be changed to hexadecimal digits (10 becomes A, 15 becomes F, etc.).
If you prefer, use Appendix 2 to look up the decimalhexadecimal equivalents. The next two examples show how. 1-12 BCD NUMBERS
A nibble is a string of 4 bits. Binary-coded-decimal (BCD) numbers express each decimal digit as a nibble. For instance, decimal 2,945 converts to a BCD number as follows:
Chapter 1
Number Systems and Codes
13
2
9
4
5
t
t
t
t
0010
1001
0100
0101
As you see, each decimal digit is coded as a nibble.
Here's another example: 9,863 10 converts like this:
9
~
1001
8
~
1000
6
~
0110
3
~
0011
Therefore, 1001 1000 0110 0011 is the BCD equivalent of
9,86310.
The reverse conversion is similar. For instance, 0010
1000 0111 0100 converts as follows:
0010
~
2
1000
~
8
0111
~
7
0100
~
4
Applications
BCD numbers are useful wherever decimal information is transferred into or out of a digital system. The circuits inside pocket calculators, for example, can process BCD numbers because you enter decimal numbers through the keyboard and see decimal answers on the LED or liquidcrystal display. Other examples of BCD systems are electronic counters, digital voltmeters, and digital clocks; their circuits can work with BCD numbers.
BCD Computers
BCD numbers have limited value in computers. A few early computers processed BCD numbers but were slower and more complicated than binary computers. As previously mentioned, a computer is more than a number cruncher because it must handle names and other nonnumeric data.
In other words, a modem computer must be able to process alphanumerics (alphabet letters, numbers, and other symbols). This why modem computers have CPUs that process binary numbers rather than BCD numbers.
Comparison of Number Systems
Table 1-5 shows the four number systems we have discussed.
Each number system uses strings of digits to represent quantity. Above 9, equivalent strings appear different. For instance, decimal string 128, hexadecimal string 80, binary string 1000 0000, and BCD string 0001 0010 1000 are equivalent because they represent the same number of pebbles. Machines have to use long strings of binary or BCD numbers, but people prefer to chunk the data in either decimal or hexadecimal form. As long as we know how to
14
Digital Computer Electronics
TABLE 1-5. NUMBER SYSTEMS
Decimal Hexadecimal
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
64
128
255
0
1
2
3
4
5
6
7
8
9
A
B
c
D
E
F
10
20
40
80
FF
Binary
0000 0000
0000 0001
0000 0010
0000 0011
0000 0100
0000 0101
0000 0110
0000 0111
0000 1000
0000 1001
0000 1010
0000 1011
0000 1100
0000 1101
00001110
0000 1111
0001 0000
0010 0000
0100 0000
1000 0000
1111 1111
BCD
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0001
0000 0001
0000 0001
0000 0001
0000 0001
0000 0001
0000 0001
0000 0011
0000 0110
000 1 00 10
0010 0101
0000
0001
0010
00 11
0100
0101
0110
0 Ill
1000
1001
0000
000 1
0010
0011
0100
0101
0 110
0010
0100
1000
0101
convert from one number system to the next, we can always get back to the ultimate meaning, which is the number of pebbles being represented.
1-13 THE ASCII CODE
To get information into and out of a computer, we need to use numbers, letters, and other symbols. This implies some kind of alphanumeric code for the 1/0 unit of a computer.
At one time, every manufacturer had a different code, which led to all kinds of confusion. Eventually, industry settled on an input-output code known as the American
Standard Code for Information Interchange (abbreviated
ASCII). This code allows manufacturers to standardize
110 hardware such as keyboards, printers, video displays, and so on.
The ASCII (pronounced ask'-ee) code is a 7-bit code whose format (arrangement) is
where each X is a 0 or a 1. For instance, the letter A is coded as
1000001
Sometimes, a space is inserted for easier reading:
100 0001
TABLE 1-6. THE ASCII CODE
X3X2X1X0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
More examples are
110 0010
1100011
1100100
X6XsX4
010
011
100
101
SP
0
p
Q
R
"
#
$
%
&
2
@
A
B
3
c
s
4
D
E
F
G
H
I
T
5
6
7
8
9
*
u v w
X
y
z
J
+
K
<
>
?
L
M
N
0
110 a b c d e f g h
111 p q r s
X
j k 010 0000
(space)
1-11
With an ASCII keyboard, each keystroke produces the
ASCII equivalent of the designated character. Suppose you type 0
(A)
PRINT X
What is the output of an ASCII keyboard?
SOLUTION
Table 1-6 includes the ASCII code for lowercase letters.
The letter a is coded as
110 0001
($)
(+)
(=)
In Table 1-6, SP stands for space (blank). Hitting the space bar of an ASCII keyboard sends this into a microcomputer:
EXAMPLE
Table 1-6 shows the ASCII code. Read the table the same as a graph. For instance, the letter A has an X 6X5X 4 of 100 and an X 3X 2X 1X 0 of 0001. Therefore, its ASCII code is
100 0001
010 0100
0101011
0111101
z
m n (d)
and so on.
Also look at the punctuation and mathematical symbols.
Some examples are
u v w y (b)
(c)
P (101 0000), R (101 0010), I (100 1001), N (100 1110),
T (101 0100), space (010 0000), X (101 1000).
(a)
GLOSSARY address Each memory location has an address, analogous to a house address. Using addresses, we can tell the computer where desired data is stored. alphanumeric Letters, numbers, and other symbols. base The number of digits (basic symbols) in a number system. Decimal has a base of 10, binary a base of 2, and hexadecimal a base of 16. Also called the radix. bit An abbreviation for binary digit. byte A string of 8 bits. The byte is the basic unit of binary information. Most computers process data with a length of
8 bits or some multiple of 8 bits. central processing unit The control section and the arithmetic-logic section. Abbreviated CPU. chip An integrated circuit. chunking Replacing a longer string by a shorter one. data Names, numbers, and any other information needed to solve a problem. digital Pertains to anything in the form of digits, for example, digital data.
hardware The electronic, magnetic, and mechanical devices used in a computer. hexadecimal A number system with a base of 16. Hexadecimal numbers are used in microprocessor work. input-output Abbreviated 110. The input and output sections of a computer are often lumped into one unit known as the 1/0 unit. microcomputer A computer that uses a microprocessor for its central processing unit (CPU). microprocessor A CPU on a chip. It contains the control and arithmetic-logic sections. Sometimes abbreviated MPU
(microprocessor unit). nibble A string of 4 bits. Half of a byte. program A sequence of instructions that tells the computer how to process the data. Also known as software. register A group of electronic, magnetic, or mechanical devices that store digital data. software Programs. string A group of digits or other symbols.
Chapter 1 Number Systems and Codes
15
SELF-TESTING REVIEW
Read each of the following and provide the missing words.
Answers appear at the beginning of the next question.
1.
2.
3.
4.
5.
6.
Binary means
. Binary numbers have a base of 2. The digits used in a binary number system are and - - - (two; 0, 1) Names, numbers, and other information needed to solve a problem are called _ _ __
The
is a sequence of instructions that tells the computer how to process the data.
(data, program) Computer ICs work reliably because they are based on design. When a transistor is cut off or saturated, transistor
_ _ _ _ have almost no effect.
(two-state, variations) A is a group of devices that store digital data. is an abbreviation for binary digit. A byte is a string of
_ _ _ _ bits.
(register, Bit, 8) The control and arithmetic-logic
(CPU). A microsections are called the processor is a CPU on a chip. A microcomputer is a computer that uses a for its CPU.
(central processing unit, microprocessor) The abbreviation K indicates units of approximately 1 ,000 or precisely 1,024. Therefore, 1K means 1,024, 2K means 2,048, 4K means
, and 64K means _ _ __
(4,096, 65,536) The hexadecimal number system is widely used in analyzing and programming - - The hexadecimal digits are 0 to 9 and A to - - The main advantage of hexadecimal numbers is the ease of conversion from hexadecimal to - - - and vice versa.
8. (microprocessors, F, binary) A typical microcomputer may have up to 65,536 registers in its memory. Each of these registers, usually called a---· stores 1 byte. Such a memory is specified as a 64kilobyte memory, or simply a memory. 9. (memory location, 64K) Binary-coded-decimal
(BCD) numbers express each decimal digit as a - - ·
BCD numbers are useful whenever information is transferred into or out of a digital system. Equipment using BCD numbers incl~d~s pocket calculators, electronic counters, and digital voltmeters. 10. (nibble, decimal) The ASCII code is a 7-bit code for (letters, numbers, and other symbols).
11. (alphanumerics) With the typical microcomputer, you enter the program and data with typewriter keyboard that converts each character into ASCII code. 7.
PROBLEMS
1-1.
1-2.
1-3.
1-4.
How many bytes are there in each of these numbers?
a. 1100 0101
b. 1011 1001 0110 1110
c. 1111 1011 0111 0100 1010
What are the equivalent decimal numbers for each of the following binary numbers: 10, 110, 111,
1011, llOO, and 1110?
What is the base for each of these numbers?
a. 348 10
b. 1100 01012
c. 23125
d. F4C3I6
Write the equation
2
1-5.
1-6.
16
+
2
=;
4
using binary numbers.
What is the decimal equivalent of 2 10 ? What does
4K represent? Express 8,192 inK units.
A 4-bit register has output voltages of high-lowhigh-low. What is the binary number stored in the register? The decimal equivalent?
Digital Computer Electronics
oeoeooee
Fig. 1-8 An 8-bit LED display.
1-7.
1-8.
1-9.
Figure 1-8 shows an 8-bit LED display. A light circle means that a LED is ON (binary 1) and a dark circle means a LED is OFF (binary 0). What is the binary number being displayed? The decimal equivalent?
Convert the following binary numbers to decimal numbers: a. 00111
b. 11001
c. 10ll0
d. 11110
Solve the following equation for x:
x 10
1-10.
""
110010012
An 8-bit transistor register has this output: low-high-low-high-low-high-low-high What is the equivalent decimal number being stored? Fig. 1-9 An 8-bit core register.
1-11.
In Fig. 1-9 clockwise flux stands for binary 1 and counterclockwise flux for binary 0. What is the binary number stored in the 8-bit core register?
Convert this byte to an equivalent decimal number. r-----------~----------~----------~~--------~~~+5V
Fig. 1-10 A 5-bit switch register.
'_,'
1-12.
1-13.
1-14.
1-15.
1-16.
1-17.
1-18.
1-19.
1-20.
Figure 1-10 shows a 5-bit switch register. By opening and closing the switches you can set up different binary numbers. As usual, high output voltage stands for binary 1 and low output voltage for binary 0. What is the binary number stored in the switch register? The equivalent decimal number?
Convert decimal 56 to its binary equivalent.
Convert 72 10 to a binary number.
An 8-bit transistor register stores decimal 150.
What is the binary output of the register?
How would you set the switches of Fig. 1-10 to get a decimal output of 27?
A hexadecimal odometer displays F52A. What are the next six readings?
The reading on a hexadecimal odometer is 27FF.
What is the next reading? Miles later, you see a reading of 8AFC. What are the next six readings?
Convert each of the following hexadecimal numbers to binary:
a. FF
b. ABC
c. CD42
d. F329
Convert each of these binary numbers to an equivalent hexadecimal number:
a. 1110 1000
b. 1100 1011
c. 1010 1111 0110
d. 1000 1011 1101 0110
1-21.
Here is a program written for the 8085 microprocessor:
Address
Hex Contents
2000
2001
2002
2003
2004
1-22.
1-23.
1-24.
1-25.
3E
OE
D3
20
76
Convert the hex contents to equivalent binary numbers. Convert each of these hexadecimal numbers to its decimal equivalent:
a. FF
b. A4
c. 9B
d. 3C
Convert the following hexadecimal numbers to their decimal equivalents:
a. OFFF
b. 3FFF
c. 7FE4
d. B3D8
A microcomputer has memory locations from
0000 to OFFF. Each memory location stores 1 byte. In decimal, how many bytes can the microcomputer store in its memory? How many kilobytes is this?
Suppose a microcomputer has memory locations from 0000 to 3FFF, each storing l byte. How
Chapter 1
Number Systems and Codes
17
1-26.
1-27.
1-28.
1-29.
1-30.
18
many bytes can the memory store? Express this in kilobytes. A microcomputer has a 32K memory. How many bytes does this represent? If 0000 stands for the first memory location, what is the hexadecimal notation for the last memory location?
If a microcomputer has a 64K memory, what are the hexadecimal notations for the first and last memory locations?
Convert the following decimal numbers to hexadecimal:
a. 4,095
b. 16,383
c. 32,767
d. 65,535
Convert each of the following decimal numbers to hexadecimal numbers:
a. 238
b. 7,547
c. 15,359
d. 47,285
How many nibbles are there in each of the following:
a. 10000111'
b. 1001 000,0 01QO ooi 1 . r c. 0~16'! 1oo 1 o111 oo io 01 '10 011 o
Digital Computer Electronics
.-,
· 1-31.
1-32.
1-33.
1-34.
If the numbers in Prob. 1-30 are BCD numbers, what are the equivalent decimal numbers?
What is the ASCII code for each of the following:
a. 7
b. w
c. f
d. y
Suppose you type LIST with an ASCII keyboard.
What is the binary output as you strike each letter? For each of the following rows, provide the missing numbers in the bases indicated.
Base 2
a.
b.
c.
200
3CD
125
1101 1110 1111
FFFF
f.
g.
Base 16
0100 0001
d.
e.
Base 10
2,000
=D-
2
GATES
For centuries mathematicians felt there was a connection between mathematics and logic, but no one before George
Boole could find this missing link. In 1854 he invented symbolic logic, known today as boolean algebra. Each variable in boolean algebra has either of two values: true or false. The original purpose of this two-state algebra was to solve logic problems.
Boolean algebra had no practical application until 1938, when Claude Shannon used it to analyze telephone switching circuits. He let the variables represent closed and open relays. In other words, Shannon came up with a new application for boolean algebra. Because of Shannon's work, engineers realized that boolean algebra could be applied to computer electronics.
This chapter introduces the gate, a circuit with one or more input signals but only one output signal. Gates are digital (two-state) circuits because the input and output signals are either low or high voltages. Gates are often called logic circuits because they can be analyzed with boolean algebra.
An inverter is also called a NOT gate because the output is not the same as the input. The output is sometimes called the complement (opposite) of the input.
+5V
1 kS1
{Jdc? 10
(0 or +5 V)
Fig. 2-1 Example of inverter design.
TABLE 2-2
TABLE 2-1
High
Low
Low
High
2-1 INVERTERS
An inverter is a gate with only one input signal and one output signal; the output state is always the opposite of the input state.
Transistor Inverter
Figure 2-1 shows a transistor inverter. This common-emitter amplifier switches between cutoff and saturation. When VrN is low (approximately 0 V), the transistor cuts off and VouT is high. On the other hand, a high VrN saturates the transistor, forcing VoUT to go low.
Table 2-1 summarizes the operation. A low input produces a high output, and a high input results in a low output.
Table 2-2 gives the same information in binary form; binary
0 stands for low voltage and binary 1 for high voltage.
0
0
IIIN
--<{>--
VOUT
(b)
VIN
-{::>o--C:>o-(c)
V OUT
IIIN--{:>-- VouT
(d)
Fig. 2-2 Logic symbols: (a) inverter; (b) another inverter symbol;
(c) double inverter; (d) buffer.
Inverter Symbol
Figure 2-2a is the symbol for an inverter of any design.
Sometimes a schematic diagram will use the alternative symbol shown in Fig. 2-2b; the bubble (small circle) is on
19
---------
the input side. Whenever you see either of these symbols,
remember that the output is the complement of the input.
Noninverter Symbol
If you cascade two inverters (Fig. 2-2c), you get a noninverting amplifier. Figure 2-2d is the symbol for a noninverting amplifier. Regardless of the circuit design, the action is always the same: a low input voltage produces a low output voltage, and a high input voltage results in a high output voltage.
The main use of noninverting amplifier is buffering
(isolating) two other circuits. More will be said about buffers in a later chapter.
EXAMPLE
2-1
A
8
c
6~btt
register
D
E
F
1
0
A
Fig. 2-4 A 2-input diode
Diode
OR
OR
gate.
Gate
Figure 2-4 shows one way to build an OR gate. If both inputs are low, the output is low. If either input is high, the diode with the high input conducts and the output is high. Because of the two inputs, we call this circuit a 2input OR gate.
Table 2-3 summarizes the action; binary 0 stands for low voltage and binary 1 for high voltage. Notice that one or more high inputs produce a high output; this is why the circuit is called an OR gate.
0
0
1
6bit register 0
0
o
1
(a)
"»---"
(b)
Fig. 2-5 A 3-input diode
OR
gate.
More than Two Inputs
Fig. 2-3 Example 2-1.
Figure 2-3a has an output, A to F, of 100101. Show how to complement each bit.
SOLUTION
Easy. Use an inverter on each signal line (Fig. 2-3b). The final output is now 011010.
A hex inverter is a commercially available IC containing six separate inverters. Given a 6-bit register like Fig. 2-3a, we can connect a hex inverter to complement each bit as shown in Fig. 2-3b.
One more point. In Fig. 2-3a the bits may represent a coded instruction, number, letter, etc. To convey this variety of meaning, a string of bits is often called a binary word or simply a word. In Fig. 2-3b the word 100101 is complemented to get the word 011010.
2-2 OR GATES
The OR gate has two or more input signals but only one output signal. If any input signal is high, the output signal is high.
20
Digital Computer Electronics
Figure 2-5 shows a 3-input OR gate. If all inputs are low, all diodes are off and the output is low. If 1 or more inputs are high, the output is high.
Table 2-4 summarizes the action. A table like this is called a truth table; it lists all the input possibilities and the corresponding outputs. When constructing a truth table, always list the input words in a binary progression as shown
(000, 001, 010, ... , 111); this guarantees that all input possibilities will be accounted for.
An OR gate can have as many inputs as desired; add one diode for each additional input. Six diodes result in a 6-
input OR gate, nine diodes in a 9-input OR gate. No matter how many inputs, the action of any OR gate is summarized like this: one or more high inputs produce a high output.
Bipolar transistors and MOSFETs can also be used to build OR gates. But no matter what devices are used, OR gates always produce a high output when one or more inputs are high. Figure 2-6 shows the logic symbols for
2-, 3-, and 4-input OR gates.
=D-(a)
(b)
(c)
Fig. 2-6 OR-gate symbols.
EXAMPLE
2-3
How many inputs words are in the truth table of an 8-input gate? Which input words produce a high output?
OR
SOLUTION
The input words are 0000 0000, 0000 000 1, . . . , 1111
1111. With the formula of the preceding example, the total number of input words is 2" = 28 = 256.
In any OR gate, 1 or more high inputs produce a high output. Therefore, the input word of 0000 0000 results in a low output; all other input words produce a high output.
EXAMPLE
EXAMPLE
2-2
+5
Show the truth table of a 4-input
OR
gate.
2-4
v
0
1
SOLUTION
2
Let Y stand for the output bit and A, B, C, D for input bits.
Then the truth table has input words of 0000, 0001, 0010,
... , 1111, as shown in Table 2-5. As expected, output Y is 0 for input word 0000; Y is 1 for all other input words.
As a check, the number of input words in a truth table always equals 2", where n is the number of input bits. A
2-input OR gate has a truth table with 22 or 4 input words; a 3-input OR gate has 23 or 8 input words; and a 4-input
OR gate has 24 or 16 input words.
3
4
5
6
7
8 _L_
...
9 _L_
TABLE 2-5. FOUR-INPUT
GATE
OR
A
B
c
D
y
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
0
y3
0
0
1
0
0
0
0
1
0
0
1
0
0
0
1
0
1
0
y2
Fig. 2-7 Decimal-to-binary encoder.
The switches of Fig. 2-7 are push-button switches like those of a pocket calculator. The bits out of the OR gates form a
4-bit word, designated Y3 Y2 Y 1Y0 • What does the circuit do? SOLUTION
Figure 2-7 is a decimal-to-binary encoder, a circuit that converts decimal to binary. For instance, when push button
3 is pressed, the Y 1 and Y0 OR gates have high inputs; therefore, the output word is
Chapter 2
Gates
21
If button 5 is keyed, the Y2 and Y 0
OR
gates have high
inputs and the output word becomes
When switch 9 is pressed,
Check the other input switches to convince yourself that the output word always equals the binary equivalent of the switch being pressed.
2-3 AND GATES
Table 2-6 summarizes the action. As usual, binary zero stands for low voltage and binary 1 for high voltage. As you see, A and B must be high to get a high output; this is why the circuit is called an AND gate.
+5
The AND gate has two or more input signals but only one output signal. All inputs must be high to get a high output.
+5
v
+5
v
v
c o-----too--___J
Fig. 2-9 A 3-input
-
y
AND
gate.
..,__._-{) y
More than Two Inputs
-
(a)
+5
+5
(b)
v
+5
v
+5
v
+5
v
v
y
(c)
(d)
Fig. 2-8 A 2-input AND gate. (a) circuit; (b) both inputs low; (c) I low input, I high; (d) both inputs high.
Diode AND Gate
Figure 2-8a shows one way to build an AND gate. In this circuit the inputs can be either low (ground) or high ( + 5
V). When both inputs are low (Fig. 2-Sb), both diodes conduct and pull the output down to a low voltage. If one of the inputs is low and the other high (Fig. 2-Sc), the diode with the low input conducts and this pulls the output down to a low voltage. The diode with the high input, on the other hand, is reverse-biased or cut off, symbolized by the dark shading in Fig. 2-Sc.
When both inputs are high (Fig. 2-Sd), both diodes are cut off. Since there is no current in the resistor, the supply voltage pulls the output up to a high voltage ( + 5 V).
22
Digital Computer Electronics
Figure 2-9 is a 3-input AND gate. If all inputs are low, all diodes conduct and pull the output down to a low voltage.
Even one conducting diode will pull the output down to a low voltage; therefore, the only way to get a high output is to have all inputs high. When all inputs are high, all diodes are nonconducting and the supply voltage pulls the output up to a high voltage.
Table 2-7 summarizes the 3-input AND gate. The output is 0 for all input words except 111. That is, all inputs must be high to get a high output.
AND gates can have as many inputs as desired; add one diode for each additional input. Eight diodes, for instance, result in an 8-input AND gate; sixteen diodes in a 16-input
TABLE 2-7. THREEINPUT AND GATE
A
B
c
y
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
For instance, when
(a)
ENABLE = 0
(b)
(c)
Fig. 2-10 AND-gate symbols.
AND gate. No matter how many inputs an AND gate has, the action can be summarized like this: All inputs must be high to get a high output.
Figure 2-10 shows the logic symbols for 2-, 3-, and 4input AND gates.
EXAMPLE
each AND gate has a low ENABLE input. No matter what the register contents, the output of each AND gate must be low. Therefore, the final word is
As you see, a low ENABLE blocks the register contents from the final output.
On the other hand, when
2-5
Describe the truth table of an 8-input
AND
ENABLE
gate.
=
the output of each AND gate depends on the data inputs (A,
B, C, ... ); a low data input results in a low output, and
SOLUTION
The input words are from 0000 0000 to 1111 1111, following the binary progression. The total number of input words is
a high data input in a high output. For example, if ABCDEF
100100, a high ENABLE gives
2" = 28 = 256
The first 255 input words produce a 0 output. Only the last word, 1111 1111, results in a 1 output. This is because all inputs must be high to get a high output.
In general, a high ENABLE transmits the register contents to the final output to get
ABCDEF
2-6
EXAMPLE
2-4 BOOLEAN ALGEBRA
6~bit
A
8
C
register
D
E
F
As mentioned earlier, Boole invented two-state algebra to solve logic problems. This new algebra had no practical use until Shannon applied it to telephone switching circuits.
Today boolean algebra is the backbone of computer circuit analysis and design.
Inversion Sign
Fig. 2-11 Using AND gates to block or transmit data.
The 6-bit register of Fig. 2-11 stores the word ABCDEF.
The ENABLE input can be low or high. What does the circuit do?
In boolean algebra a variable can be either a 0 or a 1. For digital circuits, this means that a signal voltage can be either low or high. Figure 2-12 is an example of a digital circuit because the input and output voltages are either low or high. Furthermore, because of the inversion, Y is always the complement of A.
SOLUTION
Fig. 2-12 Inverter.
One use of AND gates is to transmit data when certain conditions are satisfied. In Fig. 2-11 a low ENABLE blocks the register contents from the final output, but a high
ENABLE transmits the register contents.
A word equation for Fig. 2-12 is
Y
=
NOT
A
(2-1)
Chapter 2
----
Gates
23
-------------------------
If A is 0,
In boolean algebra the
Y =NOT 0
Y = NOT 1 = 0
In boolean algebra, the overbar stands for the NOT operation. This means that Eq. 2-1 can be written
Y=A
Y=A+B=O+O=O
If A
0 and B = 1,
Y
gate.
Sign
A word equation for Fig. 2-13 is
(2-3)
0 OR 0 = 0
because 0 comes out of an OR gate when both inputs are
Os.
As another example, if A = 0 and B = I,
Y
Fig. 2-14
AND
24
gate.
A word equation for Fig. 2-14 is
Y =A AND B
(2-5)
In boolean algebra the multiplication sign stands for the
AND operation. Therefore, Eq. 2-5 can be written
Y =A· B or simply
1'
Y
AND
Sign
Y = I OR 0
1 and B
0,
:=o--y
= 0 OR 1 = 1
because 1 comes out of an OR gate when either input is 1.
Similarly, if A = 1 and B = 0,
If A
1 = 1
because 1 ORed with 1 gives 1.
Don't let the new meaning of the + sign bother you.
There's nothing unusual about symbols having more than one meaning. For instance, "pot" may mean a cooking utensil, a flower container, the money wagered in a card game, a derivative of cannabis sativa and so forth; the intended meaning is clear from the sentence it's used in.
Similarly, the + sign may stand for ordinary addition or
OR addition; the intended meaning comes across in the way it's used. If we're talking about decimal numbers, + means ordinary addition, but when the discussion is about logic circuits, + stands for OR addition.
Given the inputs, you can solve for the output. For instance, if A = 0 and B = 0,
=
+
Y=A+B=l+l
because NOT 1 is 0.
Y
= 0
If both inputs are high,
Y=A=l=O
ORB
A+B
Y=A+B=l+O=l
because NOT 0 is 1. On the other hand, if A is I,
Y =A
=
because 0 ORed with 1 results in 1 . If A = 1 and B
Y=A=O=l
OR
(2-4)
Read this as '' Y equals A OR B.'' Equation 2-4 is the standard way to write the output of an OR gate.
Given the inputs, you can substitute and solve for the output. For instance, if A = 0 and B = 0,
(2-2)
Read this as '' Y equals NOT A'' or '' Y equals the complement of A." Equation 2-2 is the standard way to write the output of an inverter.
Using the equation is easy. Given the value of A, substitute and solve for Y. For instance, if A is 0,
OR
sign stands for the OR operation.
Y=A+B
On the other hand, if A is 1,
Fig. 2-13
+
In other words, Eq. 2-3 can be written
=
I OR 1
Digital Computer Electronics
y = AB
(2-6)
Read this as '' Y equals A AND B.'' Equation 2-6 is the standard way to write the output of an AND gate.
Given the inputs, you can substitute and solve for the output. For instance, if both inputs are low,
The distinction between italic and roman notation will become clearer when we get to computer analysis.
Y=AB=O·O=O
A final point. Positive logic means that I stands for the more positive of the two voltage levels. Negative logic means that 1 stands for the more negative of the two voltage levels. For instance, if the two voltage levels are 0 and -5
V, positive logic would have 1 stand for 0 V and 0 for - 5
V, whereas negative logic would have I stand for - 5 V and 0 for 0 V.
Ordinarily, people use positive logic with positive supply voltages and negative logic with negative supply voltages.
Throughout this book, we will be using positive logic.
because 0 ANDed with 0 gives 0. If A is low and B is high,
Y=AB=O·!=O
because 0 comes out of an AND gate if any input is 0. If A is 1 and B is 0,
Y=AB=l·O
0
When both inputs are high,
Positive and Negative Logic
EXAMPLE
2-7
Y=AB=l·l
because 1 ANDed with 1 gives 1.
(a)
Decision-Making Elements
The inverter, OR gate, and AND gate are often called decision-making elements because they can recognize some input words while disregarding others. A gate recognizes a word when its output is high; it disregards a word when its output is low. For example, the AND gate disregards all words with one or more Os; it recognizes only the word whose bits are all ls.
(b)
Fig. 2-15 Logic circuits.
What is the boolean equation for Fig. 2-15a? The output if both inputs are high?
SOLUTION
Notation
In later equations we need to distinguish between bits that are ANDed and bits that are part of a binary word. To do this we will use italic (slanted) letters (A, B, Y, etc.) for
ANDed bits and roman (upright) letters (A, B, Y, etc.) for bits that form a word.
For example, Y3Y2Y 1Y0 stands for the logical product
(ANDing) of Y 3 , Y2 , Y1 , and Y0 • If Y 3 = 1, Y2 = 0, Y1 =
0, and Y0 = 1, the product Y3 Y2 Y 1Y0 will reduce as follows:
Y 3 Y 2 Y I Y0 = 1 · 0 · 0 · 1 = 0
A is inverted before it reache~ the OR gate; therefore, the upper input to the OR gate is A. The final output is
Y=A+B
This is the boolean equation for Fig. 2-15a.
To find the output when both inputs are high, either of two approaches can be used. First, you can substitute directly into the foregoing equation and solve for Y
f\j· 1. ·r ' ,,
Y=A+B=l+l=O+l=I
In this case, the italic letters represent bits that are being
ANDed.
On the other hand, Y3 Y2 Y 1Y0 is our notation for a 4-bit word. With the Y values just given, we can write
Alternatively, you can analyze the operation of Fig. 2-15a like this. If both inputs are high, the inputs to the OR gate are 0 and 1. Now, 0 ORed with 1 gives 1. Therefore, the final output is high.
i}
In this equation, we are not dealing with bits that are
ANDed; instead, we are dealing with bits that are part of a word. EXAMPLE
2-8
What is the boolean equation for Fig. 2-15b? If both inputs are high, what is the output?
Chapter 2
Gates
25
TABLE 2-8. TRUTH TABLE
FOR Y = AB +CD
SOLUTION
The AND gate forms the logical product AB, which is inverted to get
Y=AB
Read this as '' Y equals NOT AB'' or '' Y equals the complement of AB. ''
If both inputs are high, direct substitution into the equation gives Y=AB=1·1=1=0
A
B
c
D
y
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
I
0
0
I
I
0
0
1
I
0
0
0
I
0
I
0
I
0
I
0
I
0
1
0
1
0
0
0
0
I
0
0
0
I
0
0
0
and
D
I
I
0
0
0
0
Note the order of operations: the ANDing is done first, then the inversion.
Instead of using the equation, you can analyze Fig.
2-15b as follows. If both inputs are high, the AND gate has a high output. Therefore, the final output is low.
EXAMPLE
1
1
2-9
A
CD is 1 when
8
y
c
c
=
I
D
Both products are Is when
(a)
A= I
B = 1
C=
D = I
and
y
Therefore, the final output is high when A and B are ls, when C and D are Is, or when all inputs are Is.
Table 2-8 summarizes the foregoing analysis. From this it's clear that the circuit recognizes these input words: 0011,
011I, 10II, 1100, 110I, 1I10, and 1111.
(b)
Fig. 2-16 Logic circuits.
What is the boolean equation for Fig. 2-16a? The truth table? Which input words does the circuit recognize?
EXAMPLE
2-10
Write the boolean equation for Fig. 2-I6b. If all inputs are high, what is the output?
SOLUTION
SOLUTION
The upper AND gate forms the logical product AB, and the lower AND gate gives CD. ORing these products results in
The OR gate forms the logical sum B
ANDed with A to get
+
C. This sum is
Y = AB +CD
Y = A(B
Read this as '' Y equals AB OR CD.''
Next, look at Fig. 2-l6a. The final output is high if the
OR gate has one or more high inputs. This happens when
AB is I, CD is I, or both are Is. In turn, AB is I when
A= I
26
and
B=I
Digital Computer Electronics
+
C)
(Parentheses indicate ANDing.)
One way to find the output when all inputs are high is to substitute and solve as follows:
Y = A(B
+
C) = 1(1
+
I)
I(I)
Alternatively, you can analyze Fig. 2-l6b like this. If all inputs are high, the OR gate has a high output; therefore, both inputs to the AND gate are high. Since all high inputs to an AND gate result in a high output, the final output is high. SOLUTION
Each AND gate forms the logical product of its input signals.
The inputs to the top AND gate are A, B, C and D; therefore,
Yo= ABCD
EXAMPLE
2-11
The inputs to the next means that
AND
gate are
A, B, C and
D; this
4-bit register
B
A
~~ c c
Y 1 = ABCD
D
~ ~ ~
Analyzing the remaining gates gives
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
'
\
./
I
I
I
~
J
\
EXAMPLE
= ABCD
= ABCD
= ABCD
= ABCD
=
ABCD
= ABCD
=
ABCD
= ABCD
2-12
What does the circuit of Fig. 2-17 do?
J
SOLUTION
'
J'
I
.
L
I
Fig. 2-17 A 1-of-10 decoder.
What is the boolean equation for each Y output in Fig.
2-17?
This is a binary-to-decimal decoder, a circuit that converts from binary to decimal. For instance, when the register contents are 0011, the Y3 AND gate has all high inputs; therefore, Y 3 is high. Furthermore, register contents ofOOll mean that all other AND gates have at least one low input.
As a result, all other AND gates have low outputs. (Analyze the circuit to convince yourself.)
If the register contents change to 0100, only the Y 4 AND gate has all high inputs; therefore, only Y 4 is high. If the register contents change to 0 Ill, Y7 is the only high output.
In general, the subscript of the high output equals the decimal equivalent of the binary number stored in the register. This is why the circuit is called a binary-to-decimal decoder. The circuit of this example is also called a 4-line-to-1 0line decoder because there are 4 input lines and 10 output lines. Another name for it is a 1-of-10 decoder because only 1 of 10 output lines has a high voltage.
GLOSSARY gate A logic circuit whose output is high only when all inputs are high.
AND
boolean algebra Originally known as symbolic logic, this modem algebra uses the set of numbers 0 and I. The
Chapter 2
Gates
27
operations
OR, AND, and NOT are sometimes called union, intersection, and inversion. Boolean algebra is ideally suited
to digital circuit analysis. complement The output of an inverter. gate A logic circuit with one or more input signals but only one output signal. inverter A gate with only 1 input and 1 output. The output is always the complement of the input. Also known as a
NOT gate. logic circuit A circuit whose input and output signals are
two-state, either low or high voltages. The basic logic circuits are OR, AND, and NOT gates.
OR gate A logic circuit with 2 or more inputs and only 1 output; 1 or more high inputs produce a high output. truth table A table that shows all input and output possibilities for a logic circuit. The input words are listed in binary progression. word A string of bits that represent a coded instruction or data.
SELF-TESTING REVIEW
Read each of the following and provide the missing words.
Answers appear at the beginning of the next question.
5.
1.
2.
3.
4.
A gate is a logic circuit with one or more input signals but only output signal. These signals are either or high.
(one, low) An inverter is a gate with only _ _ __ input; the output is always in the opposite state from the input. An inverter is also called a _ _ __ gate. Sometimes the output is referred to as the complement of the input.
(1, NOT) The OR gate has two or more input signals.
, the output is high. The
If any input is number of input words in a truth table always equals
_ _ _ _ , where n is the number of input bits.
(high, 2") The gate has two or more
6.
7.
input signals. All inputs must be high to get a high output. (AND) In boolean algebra, the overbar stands for the
NOT operation, the plus sign stands for the _ _ __ operation, and the times sign for the _ _ __ operation. (OR, AND) The inverter, OR gate, and AND gate are called decision-making elements because they can recognize some input while disregarding others. A gate recognizes a word when its output is
(words, high) A binary-to-decimal decoder is also called a 4-line-to--10-line decoder because it has 4 input lines and 10 output lines. Another name for it is the 1-of-1 0 decoder because only 1 of its 10 output lines is high at a time.
PROBLEMS
2-1.
2-2.
2-3.
2-4.
2-5.
2-6.
28
How many inputs signals can a gate have? How many output signals?
If you cascade seven inverters, does the overall circuit act like an inverter or noninverter?
Double inversion occurs when two inverters are cascaded. Does such a connection act like an inverter or noninverter?
The contents of the 6-bit register in Fig. 2-3b change to 101010. What is the decimal equivalent of the register contents? The decimal equivalent out of the hex inverter?
An OR gate has 6 inputs. How many input words are in its truth table? What is the only input word that produces a 0 output?
Figure 2-18 shows a hexadecimal encoder, a circuit that converts hexadecimal to binary. Pressing each push-button switch results in a different output word Y 3Y2Y 1Y0 • Starting with switch
0, what are the output words? (NOTE: The new symbol in Fig. 2-18 is another way to draw an OR gate. Digital Computer Electronics
2-7.
In Fig. 2-18 what switches would you press to produce 0011 1001 1100 1111
2-8.
2-9.
2-10.
(Work from left to right.)
What is the 4-bit output in Fig. 2-18 when switch
A is pressed? Switch 4? Switch E? Switch 6?
An AND gate has 7 inputs. How many input words are in its truth table? What is the only input word that produces a 1 output?
Visualize the register contents of Fig. 2-19 as the word A7A 6 • • • A0 , and the final output as the word Y7Y6 • • • Y0 . What is the output word for each of the following conditions:
a. A7 A6 • • • A0 = 1100 1010, ENABLE
0.
b. A7A6 • • • A0 = 0101 1101, ENABLE
1.
c. A7 A6 • • • A0 = 1111 0000, ENABLE
1.
d. A7 A6 • • • A0 = 1010 1010, ENABLE = 0.
+5
v
0
.____________________________________________
____L_
-;;;:
-
1
I
I
r
I
l
I
Yo
Fig. 2-18 Hexadecimal encoder.
8-bit register
(a)
~=D----f>r-
y
(b)
Fig. 2-19
Fig. 2-20
2-11.
2-13.
2-12.
The 8-bit register of Fig. 2-19 stores 59 10 . What is the decimal equivalent of the final output word if ENABLE = 0? If ENABLE
I?
Answer these questions:
a. What input words does a 6-input OR gate recognize? What word does it disregard?
b. What input word does an 8-input AND gate recognize? What words does it disregard?
2-14.
2-15.
What is the boolean equation for Fig. 2-20a? The output if both inputs are high?
If all inputs are high in Fig. 2-20b, what is the output? The boolean equation for the circuit?
What is the only ABC input word the circuit recognizes? If you constructed the truth table for Fig. 2-20b, how many input words would it contain?
Chapter 2
Gates
29
A
y
l nstruct1on reyister
8
115
(a)
114
113
R1 l7 ~
A
c
...
lo
7
~
y
8
112
LOA
ADD
c
~
(b)
~
Fig. 2-21
D-
~
A
8
c
D-
y
~
D
E
SUB
STA
LOB
LOX
JMP
JAM
F
(a)
D- D~
(b)
Fig. 2-22
D-
~
D-
JAZ
JIM
JIZ
JMS
DSZ
ISZ
.....--
y
~
MIX
.....--
Fig. 2-25 A 1-of-16 decoder.
Fig. 2-23
A
8 y c
D
Fig. 2-24
30
Digital Computer Electronics
OPR
2-16.
2-17.
2-18.
2-19.
2-20.
2-21.
2-22.
What is the boolean equation for Fig. 2-21a? The output if both inputs are high?
If all inputs are high in Fig. 2-2lb, what is the output? What is the boolean equation of the circuit? What ABC input words does the circuit recognize? What is the only word it disregards?
What is the boolean equation for Fig. 2-22a? The output if all inputs are ls? If you were to construct the truth table, how many input words would it have?
Write the boolean equation for Fig. 2-22b. If all inputs are 1s, what is the output?
If both inputs are high in Fig. 2-23, what is the output? What is the boolean e'l,uation for the circuit? Describe the truth table. /
What is the boolean equation for Fig. 2-24? How many ABCD input words are in the truth table?
Which input words does the circuit recognize?
Because of the historical connection between boolean algebra and logic, some people use the words
"true" and "false" instead of "high" and
"low" when discussing logic circuits. For instance, here's how an AND gate can be described.
If any input is false, the output is false; if all inputs are true, the output is true.
a. If both inputs are false in Fig. 2-23, what is the output?
b. What is the output in Fig. 2-23 if one input is false and the other true?
c. In Fig. 2-23 what is the output if all inputs are true? 2-23.
Figure 2-25 shows a 1-of-16 decoder. The signals coming out of the decoder are labeled LDA,
ADD, SUB, and so on. The word formed by the 4 leftmost register bits is called the OP CODE. As an equation,
OP CODE = I 15 I 14I 13 I 12
If LDA is high, what does OP CODE equal?
If ADD is high, what does it equal?
When OP CODE = 1001, which of the output signals is high?
d. Which output signal is high if OP CODE =
1111?
2-24. In Fig. 2-25, list the OP CODE words and the corresponding high output signals. (Start with
0000 and proceed in binary to 1111 . )
2-25. In the following equations the equals sign means
"is equivalent to." Classify each of the following as positive or negative logic:
a. 0 = 0 V and 1 = +5 V.
b. 0 = + 5 V and 1 = 0 V.
c. 0 = -5 V and 1 = 0 V.
d. 0 = 0 V and 1 = -5 V.
2-26. In Fig. 2-25 four output lines come from the decoder. Is it possible to add more op codes without increasing the number of output lines?
2-27. How many output lines from the decoder would be needed to have 256 op codes?
a.
b.
c.
Chapter 2
Gates
31
MORE LOGIC GATES
TABLE 3-1. TWOINPUT NOR GATE
This chapter introduces NOR and NAND gates, devices that are widely used in industry. You will also learn about De
Morgan's theorems; they help you to rearrange and simplify logic circuits.
A
B
0
0
1
0
3-1 NOR GATES
1
0
0
0
0
The NOR gate has two or more input signals but only one output signal. All inputs must be low to get a high output.
In other words, the NOR gate recognizes only the input word whose bits are all Os.
Incidentally, the boolean equation for a 2-input NOR gate is Y=A+B
(a)
Fig. 3-1
NOR
gate:
(b)
(a)
logical meaning;
(b)
standard symbol.
Read this as '' Y equals NOT A OR B.'' If you use this equation, remember that the ORing is done first, then the inversion. ;~
Two-Input Gate
Figure 3-1a shows the logical structure of a NOR gate, which is an OR gate followed by an inverter. Therefore, the final output is NOT the OR of the inputs. Originally called a NOT -OR gate, the circuit is now referred to as a
NOR gate.
Figure 3-1b is the standard symbol for a NOR gate. Notice that the inverter triangle has been deleted and the small circle or bubble moved to the OR-gate output. The bubble is a reminder of the inversion that follows the oRing.
With Fig. 3-la and b the following ideas are clear. If both inputs are low, the final output is high. If one input is low and the other high, the output is low. And if both inputs are high, the output is low.
Table 3-1 summarizes the circuit action. As you see, the
NOR gate recognizes only the input word whose bits are all
Os. In other words, all inputs must be low to get a high output. 32
(3-1)
c
y
D
(a)
Fig. 3-2
NOR
gates:
(b)
(a)
3-input;
(b)
4-input.
Three-Input Gate
Regardless of how many inputs a NOR gate has, it is still logically equivalent to an OR gate followed by an inverter.
For instance, Fig. 3-2a shows a 3-input NOR gate. The 3 inputs are ORed, and the result is inverted. Therefore, the boolean equation is
Y=A+B+C
(3-2)
The analysis of Fig. 3-2a goes like this. If all inputs are low, the result of ORing is low; therefore, the final output
A~· y TABLE 3-2. THREE-INPUT
NOR GATE
A
B
c
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
A+B+C
0
1
0
0
8
0
1
0
(a)
A
y
8
Fig. 3-3 De Morgan's first theorem: (a) with inverted inputs.
is high. If one or more inputs are high, the result of oRing is high; so the final output is low.
Table 3-2 summarizes the action of a 3-input NOR gate.
As you see, the circuit recognizes only the input word whose bits are Os. In other words, all inputs must be low to get a high output.
Four-Input Gate
Figure 3-2b is the symbol for a 4-input NOR gate. The inputs are ORed, and the result is inverted. For this reason, the boolean equation is
Y=A+B+C+D
(3-3)
The corresponding truth table has input words from 0000 to 1111. Word 0000 gives a 1 output; all other words produce a 0 output. (For practice, you should construct the truth table of the 4-input NOR gate.)
3-2 DE MORGAN'S FIRST THEOREM
Most mathematicians ignored boolean algbebra when it first appeared; some even ridiculed it. But Augustus De Morgan saw that it offered profound insights. He was the first to acclaim Boole's great achievement.
Always a warm and likable man, De Morgan himself had paved the way for boolean algebra by discovering two important theorems. This section introduces the first theorem.
The First Theorem
Figure 3-3a is a 2-input NOR gate, analyzed earlier. As you recall, the boolean equation is
Y=A+B and Table 3-3 is the truth table.
NOR
gate; (b)
AND
gate
Figure 3-3b has the inputs inverted before they reach the
AND gate. Therefore, the boolean equation is
Y = AB
If both inputs are low in Fig. 3-3b, the AND gate has high inputs; therefore, the final output is high. If one or more inputs are high, one or more AND-gate inputs must be low and the final output is low. Table 3-4 summarizes these ideas. TABLE 3-3
A
B
0
0
0
1
0
TABLE 3-4
A+B
0
0
0
A
B
AB
0
0
0
1
0
0
0
0
Compare Tables 3-3 and 3-4. They're identical. This means that the two circuits are logically equivalent; given the same inputs, the outputs are the same. In other words, the circuits of Fig. 3-3 are interchangeable.
De Morgan discovered the foregoing equivalence long before logic circuits were invented. His first theorem says
A+ B
=
AB
(3-4)
The left member of this equation represents Fig. 3-3a; the right member, Fig. 3-3b. Equation 3-4 says that Fig. 3-3a and b are equivalent (interchangeable).
Bubbled AND Gate
Figure 3-4a shows an AND gate with inverted inputs. This circuit is so widely used that the abbreviated logic symbol of Fig. 3-4b has been adopted. Notice that the inverter triangles have been deleted and the bubbles moved to the
Chapter 3
More Logic Gates
33
--~---
-----
-----~----
Here's what really counts. Equation 3-5 says that a 3-
A
input NOR gate and a 3-input bubbled AND gate are equivalent y (see Fig. 3-6a). Equation 3-6 means that a 4-input NOR gate and a 4-input bubbled AND gate are equivalent (Fig.
3-6b). Memorize these equivalent circuits; they are a visual statement of De Morgan's first theorem.
Notice in Fig. 3-6b how the input edges of the NOR gate and the bubbled AND gate have been extended. This is common drafting practice when there are many input signals.
The same idea applies to any type of gate.
8
(b)
Fig. 3-4 symbol. AND
gate with inverted inputs: (a) circuit; (b) abbreviated
EXAMPLE
3-1
Prove that Fig. 3-7a and care equivalent.
AND-gate inputs. From now on, we will refer to Fig.
3-4b as a bubbled AND gate; the bubbles are a reminder of the inversion that takes place before ANDing.
(b)
(a)
Fig. 3-5 De Morgan's first theorem.
Figure 3-5 is a graphic summary of De Morgan's first theorem. A NOR gate and a bubbled AND gate are equivalent.
As shown later, because the circuits are interchangeable, you can often reduce complicated logic circuits to simpler forms. (c)
Fig. 3-7 Equivalent De Morgan circuits.
SOLUTION
More than Two Inputs
When 3 inputs are involved, De Morgan's first theorem is written A+ B
+C
=ABC
(3-5)
For 4 inputs
A + B + C + D = ABCD
(3-6)
In both cases, the theorem says that the complement of a sum equals the product of the complements.
(a)
The final NOR gate in Fig. 3-7a is equivalent to a bubbled
AND gate. This allows us to redraw the circuit as shown in
Fig. 3-7b.
Double inversion produces noninversion; therefore, each double inversion in Fig. 3-7 b cancels out, leaving the simplified circuit of Fig. 3-7c. Figure 3-7a and c are therefore equivalent.
Remember the idea. Given a logic circuit, you can replace any NOR. gate by a bubbled AND gate. Then any double inversion (a pair of bubbles in a series path) cancels out.
Sometimes you wind up with a simpler logic circuit than you started with; sometimes not.
But the point remains. De Morgan's first theorem enables you to rearrange a logic circuit with the hope of finding a simpler equivalent circuit or perhaps getting more insight into how the original circuit works.
3-3 NAND GATES
(b)
Fig. 3-6 De Morgan's first theorem: (a) 3-input circuits; (b) 4input circuits.
34
Digital Computer Electronics
The NAND gate has two or more input signals but only one output signal. All input signals must be high to get a low output. (a)
Fig. 3-8
NAND
TABLE 3-5.
TWO-INPUT
NAND GATE
(b)
TABLE 3-6. THREEINPUT NAND GATE
gate: (a) logical meaning; (b) standard symbol.
Two-Input Gate
Figure 3-8a shows the logical structure of a NAND gate, an
AND gate followed by an inverter. Therefore, the final output is NOT the AND of the inputs. Originally called a
NOT-AND gate, the circuit is now referred to as a NAND gate. Figure 3-8b is the standard symbol for a NAND gate. The inverter triangle has been deleted and the bubble moved to the AND-gate output. If one or more inputs are low, the result of ANDing is low; therefore, the final inverted output is high. Only when all inputs are high does the ANDing produce a high signal; then the final output is low.
Table 3-5 summarizes the action of a 2-input NAND gate.
As shown, the NAND gate recognizes any input word with one or more Os. That is, one or more low inputs produce a high output. The boolean equation for a 2-input NAND gate is
Y=AB
A
B
0
0
0
1
0
A
B
c
0
0
0
0
0
0
0
1
0
I
0
1
0
AB
0
0
0
ABC
1
0
Four-Input Gate
Figure 3-9b is the symbol for a 4-input NAND gate. The inputs are ANDed, and the result is inverted. Therefore, the boolean equation is
Y
=
ABCD
(3-9)
If you construct the truth table, you will have input words from 0000 to 1111 . All words from 0000 through 1110 produce a 1 output; only the word 1111 gives a 0 output.
(3-7)
Read this as '' Y equals NOT AB. '' If you use this equation, remember that the ANDing is done first then the inversion.
3-4 DE MORGAN'S SECOND
THEOREM
The proof of De Morgan's second theorem is similar to the proof given for the first theorem. What follows is a brief explanation. (a)
Fig. 3-9
NAND
The Second Theorem
(b)
When two inputs are used, De Morgan's second theorem says that
gates: (a) 3-input; (b) 4-input.
Three-Input Gate
AB=A+B
Regardless of how many inputs a NAND gate has, it's still logically equivalent to an AND gate followed by an inverter.
For example, Fig. 3-9a shows a 3-input NAND gate. The inputs are ANDed, and the product is inverted. Therefore, the boolean equation is
Y=ABC
(3-1 0)
In words, the complement of a product equals the sum of the complements. The left member of this equation represents a NAND gate (Fig. 3-lOa); the right member stands
A
(3-8)
y
Here is the analysis of Fig. 3-9a. If one or more inputs are low, the result of ANDing is low; therefore, the final output is high. If all inputs are high, the ANDing gives a high signal; so the final output is low.
Table 3-6 is the truth table for a 3-input NAND gate. As indicated, the circuit recognizes words with one or more
Os. This means that one or more low inputs produce a high output. 8
(a)
(c)
Fig. 3-10 De Morgan's second theorem: (a) NAND gate; (b) gate with inverted inputs; (c) bubbled OR gate.
Chapter 3
More Logic Gates
OR
35
for an OR gate with inverted inputs (Fig. 3-lOb). Therefore,
De Morgan's second theorem boils down to the fact that
Fig. 3-lOa and bare equivalent.
EXAMPLE 3-2
Prove that Fig. 3-13a and c are equivalent.
Fig. 3-11 De Morgan's second theorem.
(b)
(a)
Bubbled
OR
Gate
The circuit of Fig. 3-lOb is so widely used that the abbreviated logic symbol of Fig. 3-lOc has been adopted.
From now on we will refer to Fig. 3-lOc as a bubbled OR gate; the bubbles are a reminder of the inversion that takes place before ORing.
Figure 3-11 is a visual statement of De Morgan's second theorem: a NAND gate and a bubbled.oR gate are equivalent.
This equivalence allows you to replace one circuit by the other whenever desired. This may lead to a simpler logic circuit or give you more insight into how the original circuit works. ·
More than Two Inputs
When 3 inputs are involved, De Morgan's second theorem is written
ABC=A+B+C
(3-11)
If 4 inputs are used,
ABCD = A
+B +
C
+D
(3-12)
These equations say that the complement of a product equals the sum of the complements.
(a)
(b)
Fig. 3-12 De Morgan's second theorem: (a) 3-input circuits; (b)
4-input circuits.
Figure 3-12 is a visual summary of the second theorem.
Whether 3 or 4 inputs are involved, a NAND gate and a bubbled OR gate are equivalent (interchangeable).
36
Digital Computer Electronics
(c)
Fig. 3-13 Equivalent circuits.
SOLUTION
Replace the final NAND gate in Fig. 3-13a by a bubbled OR gate. This gives Fig. 3-13b. The double inversions cancel out, leaving the simplified circuit of Fig. 3-13c. Figure
3-13a and c are therefore equivalent. Driven by the same inputs, either circuit produces the same output as the other.
So if you're loaded with NAND gates, build Fig. 3-13a. If your shelves are full of AND and OR gates, build Fig.
3-13c.
Incidentally, most people find Fig. 3-13b easier to analyze than Fig. 3-13a. For this reason, if you build Fig. 3-13a, draw the circuit like Fig. 3-13b. Anyone who sees Fig.
3-13b on a schematic diagram knows that the bubbled OR gate is the same as a NAND gate and that the built-up circuit is two NAND gates working into a NAND gate.
EXAMPLE
3-3
Figure 3-14 shows a circuit called a control matrix. At first, it looks complicated, but on closer inspection it is relatively simple because of the repetition of NAND gates. De Morgan's theorem tells us that NAND gates driving NAND gates are equivalent to AND gates driving OR gates.
The upper set of inputs T1 to T6 are called timing signals; only one of them is high at a time. T1 goes high first, then
T2 , then T3 , and so on. These signals control the rate and sequence of computer operations.
The lower set of inputs LDA, ADD, SUB, and OUT are computer instructions; only one of them is high at a time.
The outputs Cp, Ep, LM, ... , to L 0 control different registers in the computer.
Answer the following questions about the control matrix:
a.
b.
c.
Which outputs are high when T1 is high?
If T 4 and LDA are high, which outputs are high?
When T6 and SUB are high, which outputs are high?
T1
T2
T3
T4
T5
T6
I ~~--------~----~---
\7LOA--t+~-t--------~-r~------~~~~------~~~-------+--~--~------~------4---+
AOO--~~~---.-----t~-t---.-----+-t-t---.----~~~~~---4---4----f-.-----~~----~--~
SUB--+f-4-t---t--~1-~1---+---.-~t-~~--~-+--~~~~~---+~~~---.-+-+--~~--+
OUT--~~ri---f---t-t~-t---t---t-+-t-t---t---+~--~--~~~~~--+-+-+---+-~+---+-~~~
LlJ,
___.[],
)
...._,
-,
-,
-, l-,
.__,
-
.J
(
L---...-.,1
Cp
1
Ep
LM
I
Eft
Fig. 3-14 Control matrix.
SOLUTION
a.
b.
c.
Visualize T 1 high. You can quickly check out each gate and realize that Ep and LM are the only high outputs. This time T 4 and LDA are high. Check each gate and you can see that LM and E1 are the only high outputs.
When T 6 and SUB are high, the high outputs are LA,
Su, and Eu.
y
(a)
:=D--y'
(b)
Fig. 3-15 (a) gate. 3-5 EXCLUSIVE-OR GATES
An
gate recognizes words with one or more ls. The gate is different; it recognizes only words that have an odd number of 1s.
OR
EXCLUSIVE-OR
Two Inputs
Figure 3-15a shows one way to build an EXCLUSIVE-OR gate, abbreviated XOR. The upper AND gate forms the product AB, and the lower AND gate gives AB. Therefore, the boolean equation is
Y=AB+AB
(3-13)
EXCLUSIVE-OR
gate. (b) A 2-input
EXCLUSIVE-OR
Here's what the circuit does. In Fig. 3-15a two low inputs mean both AND gates have low outputs; so the final output is low. If A is low and B is high, the upper AND gate has a high output; therefore, the final output is high.
Likewise, a high A and low B result in a final output that is high. If both inputs are high, both AND gates have low outputs and the final output is low.
Table 3-7 shows the truth table for a 2-input EXCLUSIVEOR gate. The output is high when A orB is high but not both; this is why the circuit is known as an EXCLUSIVE-OR gate. In other words, the output is a I only when the inputs are different.
Chapter 3
More Logic Gates
37
_ _ _ _ __ _ j_ _
-----~ - - - - - - - ---
--------
--------
r-
TABLE 3-7. TWO-
A
INPUT
8
A
B
0
0
0
1
XOR
GATE
AB
+
c
AB
J y 0
0
0
(a)
1
0
0 y Logic Symbol and Boolean Sign
(b)
Figure 3-15b is the standard symbol for a 2-input XOR gate.
Whenever you see this symbol, remember the action: the inputs must be different to get a high output.
A word equation for Fig. 3-15b is
Y =A XOR B
(3-14)
In boolean algebra the sign (f) stands for XOR addition.
This means that Eq. 3-14 can be written
Y=A(f)B
(3-15)
Fig. 3-16 A 4-input EXCLUSIVE-OR gate: (a) circuit with 2-input xoR gates; (b) logic symbol.
It's possible to substitute input values into the equation and solve for the output. For instance, if A through C are low and D is high, y = (0 (f) 0) (f) (0 (f) 1)
=08:)1
= 1
Read this as '' Y equals A XOR B.''
Given the inputs, you can substitute and solve for the output. For instance, if both inputs are low,
Y=O(f)O=O because 0 XORed with 0 gives 0. If one input is low and the other high,
Y=O(f)1=1
because 0 XORed with l produces 1. And so on.
Here's a summary of the four possible XOR additions:
08:)0
08:)1
18:)0
18:)1
0
0
Remember these four results; we will be using XOR addition when we get to arithmetic circuits.
Four Inputs
In Fig. 3-16a the upper gate produces A (f) B, while the lower gate gives C (f) D. The final gate XORs both of these sums to get
Y = (A (f) B) (f) (C (f) D)
38
Digital Computer Electronics
(3-16)
One way to get the truth table is to plow through all the input possibilities.
Alternatively, you can analyze Fig. 3-16a as follows. If all inputs are Os, the first two gates have 0 outputs; so the final gate has a 0 output. If A to C are Os and D is a 1, the upper gate has a 0 output, the lower gate has a 1 output, and the final gate has a 1 output. In this way, you can analyze the circuit action for all input words.
Table 3-8 summarizes the action. Here is an important property: each input word with an odd number of 1s produces a 1 output. For instance, the first input word to produce a 1 output is 000 I; this word has an odd number of 1s. Tl}e next word with a I output is 0010; again an odd number of 1s. A I output also occurs for these words:
0100, 0111, 1000, 10II, 1101, and 1110, all of which have an odd number of 1s.
The circuit of Fig. 3-16a recognizes words with an odd number of Is; it disregards words with an even number of
1s. Figure 3-16a is a 4-input XOR gate. In this book, we will use the abbreviated symbol of Fig. 3-16b to represent a 4-input XOR gate. When you see this symbol, remember the action: the circuit recognizes words with an odd number of Is.
Any Number of Inputs
Using 2-input XOR gates as building blocks, we can make
XOR gates with any number of inputs. For example, Fig.
TABLE 3-8. FOUR-INPUT
GATE
The first word has even parity because it contains ten 1s; the second word has odd parity because it contains eleven
1s.
XOR gates are ideal for testing the parity of a word. XOR gates recognize words with an odd number of 1s. Therefore, even-parity words produce a low output and odd-parity words produce a high output.
XOR
Comment
A
B
c
D
y
Even
Odd
Odd
Even
Odd
Even
Even
Odd
Odd
Even
Even
Odd
Even
Odd
Odd
Even
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
1
1
1
1
1
1
1
....__~-----·=-<· .<.
(a)
Fig. 3-17
XOR
oEXAMPLE
0
..,t,,
3-4
What is the output of Fig. 3-18 for each of these input words? a. 1010 1100 1000 UOO
b. 1010 1100 1000 1101
1
b
0
1
0
1
1
0
16 bits
ODD
(b)
gates: (a) 3-input; (b) 6-input.
Fig. 3-18 Odd-parity tester.
3-17a shows the abbreviated symbol for a 3-input XOR gate, and Fig. 3-17b is the symbol for a 6-input xoR gate. The final output of any xoR gate is the XOR sum of the inputs:
Y=A(jjB(jjC···
SOLUTION
a.
The word has seven 1s, an odd number. Therefore, the output signal is
(3-17)
ODD
What you have to remember for practical work is this: an XOR gate, no matter how many inputs, recognizes only words with an odd number of Is.
b.
=1
The word has eight 1s, an even number. Now
ODD= 0
Parity
Even parity means a word has an even number of Is. For instance, 110011 has even parity because it contains four
1s. Odd parity means a word has an odd number of 1s. As an example, 110001 has odd parity because it contains three 1s.
Here are two more examples:
1111000011110011
1111 0000 1111 011 1
(Even parity)
(Odd parity)
This is an example of an odd-parity tester. An evenparity word produces a low output. An odd-parity word results in a high output.
EXAMPLE
3-5
The 7-bit register of Fig. 3-19 stores the letter A in ASCII form. What does the 8-bit output word equal?
Chapter 3
More Logic Gates
39
--
- - ----'-------
Because of the 1-bit error, we receive letter C when letter
A was actually sent.
7-bit register
A6
A4
A5
A3
A2
A,
Ao
One solution is to transmit an odd-parity bit along with the data word and have an XOR gate test each received word for odd parity. For instance, with a circuit like Fig.
3-19 the letter A would be transmitted as
1100 0001
An XOR gate will test this word when it is received. If no error has occurred, the XOR gate will recognize the word.
On the other hand, if a 1-bit error has crept in, the XOR gate will disregard the received word and the data can be rejected. A final point. When errors come, they are usually 1-bit errors. This is why the method described catches most of the errors in transmitted data.
11
t
Odd-parity bit Instruction or data bits
8-bit word with odd parity
EXAMPLE
3-6
What does the circuit of Fig. 3-20 do?
Fig. 3-19 Odd-parity generator.
A
INVERT
SOLUTION
The ASCII code for letter A is
100 0001 y (see Table 1-6 for the ASCII code). This word has an even parity, which means that the XOR gate has a 0 output.
Because of the inverter, the overall output of the circuit is the 8-bit word
1100 0001
(A)
Somewhere along the line, one of the bits may be changed.
If the X1 bit changes, the received data will be
100 0011
40
SOLUTION
When INVERT
Notice that this has odd parity.
The circuit is called an odd-parity generator because it produces an 8-bit output word with odd parity. If the register word has even parity, 0 comes out of the XOR gate and the odd-parity bit is 1. On the other hand, if the register word has odd parity, a 1 comes out of the XOR gate and the oddparity bit is 0. No matter what the register contents, the odd-parity bit and the register bits form a new 8-bit word that has odd parity.
What is the practical application? Because of transients, noise, and other disturbances, 1-bit errors sometimes occur in transmitted data. For instance, the letter A may be transmitted over phone lines in ASCII form:
100 0001
Fig. 3-20
(C)
Digital Computer Electronics
=
0 and A
=
0,
Y=O(f)O=O
When IN.VERT
=
0 and A
=
1,
Y=O(f)1=1
In either case, the output is the same as A; that is,
Y=A for a low INVERT signal.
On the other hand, when INVERT
=
Y=1(f)O=
When INVERT = 1 and A = 1,
Y=1(f)1=0
1 and A
0,
This time, the output is the complement of A. As an equation, register contents. As demonstrated in Example 3-6, each
XOR gate acts like this. A low INVERT results in
Y=A for a high INVERT signal.
To summarize, the circuit of Fig. 3-20 does either of two things. It transmits A when INVERT is 0 and A when
INVERT is 1.
3-6 THE CONTROLLED INVERTER
and a high INVERT gives
So each bit is either transmitted or inverted before reaching the final output.
Visualize the register contents as a word A7A6 · • • A0 and the final output as a word Y7Y6 • • • Y0 . Then a low
INVERT means
The preceding example suggests the idea of a controlled inverter, a circuit that transmits a binary word or its I' s complement. On the other hand, a high INVERT results in
The 1 's Complement
Complement each bit in a word and the new word you get is the 1's complement. For instance, given
As a concrete example, suppose the register word is
1100 0111 the 1's complement is
Then, a low INVERT gives an output word of
0011 1000
Each bit in the original word is inverted to get the 1's complement. The Circuit
The XOR gates of Fig. 3-21 form a controlled inverter
(sometimes called a programmed inverter). This circuit can transmit the register contents or the 1's complement of the
and a high INVERT produces
The controlled inverter of Fig. 3-21 is important. Later you will see how it is used in solving arithmetic and logic problems. For now, all you need to remember is the key idea. The output word from a controlled inverter equals the
8-bit register
Fig. 3-21 Controlled inverter.
Chapter 3
More Logic Gates
41
TABLE 3-9.
TWO-INPUT
XNOR GATE
input word when INVERT is low; the output word equals the 1's complement when INVERT is high.
Boldface Notation
After you understand an idea, it simplifies discussions and equations if you use a symbol, letter, or other sign to represent the idea. From now on, boldface letters will stand for binary words.
For instance, instead of writing
we can write
A
A
B
y
0
0
0
1
0
0
0
Because of the inversion on the output side, the truth table of an XNOR gate is the complement of an XOR truth table. As shown in Table 3-9, the output is high when the inputs are the same. For this reason, the 2-input XNOR gate is ideally suited for bit comparison, recognizing when two input bits are identical. (Example 3-7 tells you more about bit comparison.)
11100110
Likewise, instead of
0001 1001 the simpler equation
y
0001 1001
can be used.
This is another example of chunking. We are replacing long strings like A7A6 • • • A0 and Y7 Y6 • • • Y0 by A and
Y. This chunked notation will be convenient when we get to computer analysis.
This is how to summarize the action of a controlled inverter: y
=
{!
when INVERT when INVERT
=
=
0
1
(Note: A boldface letter with an overbar means that each bit in the word is complemented; if A is a word, A is its l 's complement.)
(a)
Fig. 3-23
XNOR
(b)
gates: (a) 3-input; (b) 4-input.
Figure 3-23a is the symbol for a 3-input XNOR gate, and
Fig. 3-23b is the 4-input XNOR gate. Because of the inversion on the output side, these XNOR gates perform the complementary function of XOR gates. Instead of recognizing oddparity words, XNOR gates recognize even-parity words.
EXAMPLE 3-7
What
do~s
the circuit of Fig. 3-24 do?
3-7 EXCLUSIVE-NOR GATES
SOLUTION
The EXCLUSIVE-NOR gate, abbreviated XNOR, is logically equivalent to an xoR gate followed by an inverter. For example, Fig. 3-22a shows a 2-input XNOR gate. Figure
3-22b is an abbreviated way to draw the same circuit.
:=Dr-y
(a)
(b)
Fig. 3-22 A 2-input XNOR gate: (a) circuit; (b) abbreviated symbol.
42
Digital Computer Electronics
The circuit is a word comparator; it recognizes two identical words. Here is how it works. The leftmost XNOR gate compares A 5 and B 5 ; if they are the same, Y 5 is a l. The second XNOR gate compares A4 and B 4 ; if they are the same,
Y4 is a l. In tum, the remaining XNOR gates compare the bits that are left, producing a l output for equal bits and a
0 output for unequal bits.
If the words A and B are identical, all XNOR gates have high outputs and the AND gate has a high EQUAL. If words
A and B differ in one or more bit positions, the AND gate has a low EQUAL.
B register
A register
'>
EQUAL
Fig. 3-24 Word comparator.
GLOSSARY controlled inverter This circuit produces the 1's complement of the input word. One application is binary subtraction. It is sometimes called a programmed inverter.
De Morgan's theorems The first theorem says that a NOR gate is equivalent to a bubbled AND gate. The second theorem says that a NAND gate is equivalent to a bubbled
OR gate. even parity An even number of Is in a binary word.
NAND gate Equivalent to an AND gate followed by an inverter. All inputs must be high to get a low output.
NOR gate Equivalent to an OR gate followed by an inverter.
All inputs must be low to get a high output.
odd parity An odd number of Is in a binary word. parity generator A circuit that produces either an odd- or even-parity bit to go along with the data.
XNOR gate Equivalent to an EXCLUSIVE-OR gate followed by an inverter. The output is high only when the input word has even parity.
XOR gate An EXCLUSIVE-OR gate. It has a high output only when the input word has odd parity. For a 2-input
XOR gate, the output is high only when the inputs are different. SELF-TESTING REVIEW to get a low output. De Morgan's second theorem says that a NAND gate is equivalent to a bubbled
_____ gate.
Read each of the following and provide the missing words.
Answers appear at the beginning of the next question.
1.
2.
3.
A NOR gate has two or more input signals. All inputs must be to get a high output. A NOR gate recognizes only the input word whose bits are
- - - - - · The NOR gate is logically equivalent to an OR gate followed by an _ _ __
(low, Os, inverter) De Morgan's first theorem says that a NOR gate is equivalent to a bubbled _ _ __ gate. (AND) A NAND gate is equivalent to an AND gate followed by an inverter. All inputs must be _ _ __
4.
5.
(high, OR) An XOR gate recognizes only words with an number of ls. The 2-input XOR gate has a high output only when the input bits are
- - - - - · XOR gates are ideal for testing parity because even-parity words produce a _ _ _ __ output and odd-parity words produce a _ _ _ __ output. (odd, different, low, high) An odd-parity generator produces an odd-parity bit to go along with the data.
Chapter 3
More Logic Gates
43
6.
The parity of the transmitted data is
. An
XOR gate can test each received word for parity, rejecting words with parity. (odd, even) A controlled inverter is a logic circuit that transmits a binary word or its complement. 7.
(1 's) The EXCLUSIVE-NOR gate is equivalent to an
XOR gate followed by an inverter. Because of this, even-parity words produce a high output.
·'
PROBLEMS
3-1.
In Fig. 3-25a the two inputs are connected together. If A is low, what is Y? If A is high, what is Y? Does the circuit act like a noninverter or an inverter? 3-5.
The outputs in Fig. 3-27 are cross-coupled back to the inputs of the_NOR gates. If R = 0 and S =
1, what do Q and Q equal?
A---Q>--Y
(a)
A
y
8
(b)
Fig. 3-27 Cross-coupled NOR gates.
Fig. 3·25
3-6.
3-2.
3-3.
3-4.
What is the output in Fig. 3-25b if both inputs are low? If one is low and the other high? If both are high? Does the circuit act like an OR gate or an
AND gate?
Figure 3-26 shows a NOR-gate crossbar switch. If all X and Y inputs are high, which of the Z outputs is high? If all inputs are high except X 1 and Y 2 , which Z output is high? If X 2 and Y 0 are low and all other inputs are high, which Z output is high?
In Fig. 3-26, you want Z7 to be l and all other Z outputs to be 0. What values must the X and Y inputs have?
I
Y',
Fig. 3-26 NOR-gate crossbar switch.
44
Digital Computer Electronics
3-7.
3-8.
3-9.
3-10.
3-11.
3-12.
If R = __! and S = 0 in Fig. 3-27, what does Q equal? Q?
Prove that Fig. 3-28a and bare equivalent.
What is the output in Fig. 3-28a if all inputs are
Os. If all inputs are ls?
What is the output in Fig. 3-28b if all inputs are
Os. If all inputs are ls?
A NOR has 6 inputs. How many input words are in its truth table? What is the only input word that produces a 1 output?
In Fig. 3-28a how many input words are there in the truth table?
What is the output in Fig. 3-29 if all inputs are low? If all inputs are high?
(a)
(b)
/
<:_;
Fig. 3-28
b.
A
c.
y
c
d.
0
3-18.
Fig. 3-29
3-13.
3-14.
3-15.
If all inputs are low except X 2 and Y1, which
Z output is low?
8
How many words are in the truth table of Fig.
3-29. What is the value of Y for each of the following? a. ABCD = 0011
b. ABCD = 0110
c. ABCD = 1001
d. ABCD = llOO
Which ABCD input words does the circuits of
Fig. 3-29 recognize?
In Fig. 3-30a the two inputs are connected together. If A = 0 what does Y equal? If A = I , what does Y equal? Does the circuit act like a noninverter or an inverter?
If all inputs are low except X0 and Y2 , which
Z output is low?
To get a low Z 8 output, which inputs must be
high?
In Fig. 3-31, what are the outputs if R
S = I?
=
0 and
s---'-1
Fig. 3-31 Cross-coupled
3-19.
3-20.
3-21.
NAND
gates.
If R = __! and S = 0 in Fig. 3-31, what does Q equal? Q?
What is the output in Fig. 3-32a if all inputs are
Os? If all inputs are ls?
How many input words are there in the truth table of Fig. 3-32a?
WJ
)_
::
(a)
/-,
A
8
(b)
Fig. 3-30
3-16.
.--3-17.
What is the output in Fig. 3-30b if both inputs are low? If one input is low and the other high? If both are high? Does the circuit act like an OR gate or an AND gate?
Suppose the NOR gates of Fig. 3-26 are replaced by NAND gates. Then you've got a NAND-gate crossbar switch.
a. If all X and Y inputs are low, which Z output is low?
Fig. 3-32
Chapter 3
More Logic Gates
45
\
3-22.
Prove that Fig. 3-32a and b are equivalent.
3·23. What is the output in Fig. 3-33 if all inputs are
3-24.
3-25.
low? If they are all high?
How many words are in the truth table of Fig.
3-33? What does Y equal for each of the following:
a. ABCDE = OOlll
b. ABCDE = 10110
c. ABCDE = 11010
d. ABCDE = 101ol
In Fig. 3-34 the inputs are T4 , JMP, JAM, JAZ,
AM, and Az; the output is Lp. What is the output for each of these input conditions?
a. All inputs are Os.
b. All inputs are low except T4 and JMP.
3-26.
c.
All inputs are low except T 4 , JAZ, and Az.
d.
The only high inputs are T4 , JAM, and AM.
Figure 3-35 shows the control matrix discussed in
Example 3-3. Only one of the timing signals T 1 to
T6 is high at a time. Also, only one of the instructions, LDA to OUT, is high at a time. Which are the high outputs for each of the following conditions?
g. T 5 and ADD high
a. T 1 high
b. T 2 high
h. T6 and ADD high
c. T 3 high
i. T4 and SUB high
j. T 5 and SUB high
d. T4 and LDA high
k. T6 and SUB high
e. T 5 and LDA high
1. T4 and OUT high
f. T4 and ADD high
JMP
JAM
JAZ
y
Fig. 3-33
Fig. 3-34
I
I
~
LOA
ADD
SUB
OUT
Q_On
~e~-
~~
"---Jl,.
I
Cp
I
Ep
y
LM
I
ER
Fig. 3-35 Control matrix.
46
Digital Computer Electronics
~0
~~
I
'--
~- LJ= ~) c
p.~
I
19 L)= ~)
MI
3-27.
Figure 3-36 shows a binary-to-Gray-code converter. (Gray code is a special code used in analog-to-digital conversions.) The input word is
X4 X3 • • • X0 , and the output word is Y4 Y3 • • •
Y0 • What does the output word equal for each of these inputs?
a. X4X3 • • • X0 = 10011
b. X4X 3 • • • Xo = 01110
c. X4X3 • • • Xo = 10101
d. X4 X3 • • • Xo = 11100
i
}<)
x3
1
A
CARRY
SUM
Fig. 3-37
3-32.
3-33.
y4
y3·
y2
y1
3-34.
Fig. 3-36 Binary-tcr-Gray-code converter.
3-28.
3-29.
3-30.
3-31.
How many input words are there in the truth table of an 8-input xoR gate?
How can you modify Fig. 3-19 so that it produces an 8-bit output word with even parity?
In the controlled inverter of Fig. 3-21, what is the output word Y for each of these conditions?
a. A = 1100 1111 and INVERT = 0
b. A = 0101 0001 and INVERT = 1
c. A = 1110 1000 and INVERT = 1
d. A = 1010 0101 and INVERT = 0
The inputs A and B of Fig. 3-37 produce outputs of CARRY and SUM. What are the values of
CARRY and SUM for each of these inputs?
a. A = 0 and B = 0
b. A = 0 and B = 1
c. A
1 and B = 0
d. A = 1 and B = 1
8
I
3-35.
In Fig. 3-37, what is the boolean equation for
CARRY? For SUM?
What is the 1's complement for each of these numbers? a. llOO 0011
b. 1010 1111 0011
c. 1110 0001 1010 0011
d. 0000 1111 0010 1101
What is the output of a 16-input XNOR gate for each of these input words?
a. 0000 0000 0000 1111
b. 1111 0101 1l10 llOO
c. 0101 1100 0001 0011
d. 111100001010 0110
The boolean equation for a certain logic circuit is
Y = AB + CD + AC. What does Y equal for each of the following:
a. ABCD = 0000
b. ABCD = 0101
c. ABCD = 1010
d. ABCD = 1001
'
'
0
Chapter 3
More Logic Gates
47
TTL CIRCUITS
In 1964 Texas Instruments introduced transistor-transistor logic (TTL), a widely used family of digital devices. TTL is fast, inexpensive, and easy to use. This chapter concentrates on TTL because once you are familiar with it, you can branch out to other logic families and technologies.
means that you can connect the output of one device to the input of another). Compatibility permits a large number of different combinations.
Bipolar Families
In the bipolar category are these basic families:
4-1 DIGITAL INTEGRATED
CIRCUITS
Using advanced photographic techniques, a manufacturer can produce miniature circuits on the surface of a chip (a small piece of semiconductor material). The finished network is so small you need a microscope to see the connections. Such a circuit is called an integrated circuit
(IC) because the components (transistors, diodes, resistors) are an integral part of the chip. This is different from a discrete circuit, in which the components are individually connected during assembly.
DTL
TTL
ECL
Diode-transistor logic
Transistor-transistor logic
Emitter-coupled logic
DTL uses diodes and transistors; this design, once popular, is now obsolete. TTL uses transistors almost exclusively; it has become the most popular family of SSI and MSI chips. ECL, the fastest logic family, is used in high-speed applications. MOS Families
In the MOS category are these families:
Levels of Integration
Small-scale integration (SSI) refers to ICs with fewer than
12 gates on the same chip. Medium-scale integration (MSI) means from 12 to 100 gates per chip. And large-scale integration (LSI) refers to more than 100 gates per chip.
The typical microcomputer has its microprocessor, memory, and 1/0 circuits on LSI chips; a number of SSI and MSI chips are used to support the LSI chips.
Technologies and Families
The two basic technologies for manufacturing digital ICs are bipolar and MOS. The first fabricates bipolar transistors on a chip; the second, MOSFETS. Bipolar technology is preferred for SSI and MSI because it is faster. MOS technology dominates the LSI field because more MOSFETs can be packed on the same chip area.
A digital family is a group of compatible devices with the same logic levels and supply voltages ("compatible"
48
PMOS
NMOS
CMOS
p-Channel MOSFETs n-Channel MOSFETs
Complementary MOSFETs
PMOS, the oldest and slowest type, is becoming obsolete.
NMOS dominates the LSI field, being used for microprocessors and memories. CMOS, a push-pull arrangement of n- and p-channel MOSFETs, is extensively used where low power consumption is needed, as in pocket calculators, digital wristwatches, etc.
4-2 7400 DEVICES
The 7400 series, a line of TTL circuits introduced by Texas
Instruments in 1964, has become the most widely used of all bipolar ICs. This TTL family contains a variety of SSI and MSI chips that allow you to build all kinds of digital circuits and systems.
r-------.-------~--~+5V
diode of Q3 reverse-biased. In this way, only Q4 conducts when the output is low.
Totem-Pole Output
Why are totem-pole transistors used? Because they produce a low output impedance. Either Q 3 acts like an emitter follower (high output) or Q4 is saturated (low output).
Either way, the output impedance is very low. This is important because it reduces the switching time. In other words, when the output changes from low to high, or vice versa, the low output impedance implies a short RC time constant; this short time constant means that the output voltage can change quickly from one state to the other.
A
8
Fig. 4-1 Standard TTL
NAND
gate.
Propagation Delay Time and Power Dissipation
Standard TTL
Figure 4-1 shows a TTL NAND gate. The multiple-emitter input transistor is typical of all the gates and circuits in the
7400 series. Each emitter acts like a diode; therefore, Q 1 and the 4-k!l resistor act like a 2-input AND gate. The rest of the circuit inverts the signal; therefore, the overall circuit acts like a 2-input NAND gate.
The output transistors (Q 3 and Q4 ) form a totem-pole connection, typical of most TTL devices. Either one or the other is on. When Q3 is on, the output is high; when Q4 is on, the output is low. The advantage of a totem-pole connection is its low output impedance.
Ideally, the input voltages A and B are either low
(grounded) or high (5 V). If A or B is low, Q 1 saturates.
This reduces the base voltage of Q2 to almost zero.
Therefore, Q2 cuts off, forcing Q4 to cut off. Under these conditions, Q3 acts like an emitter follower and couples a high voltage to the output.
On the other hand, when both A and B are high, the collector diode of Q 1 goes into forward conduction; this forces Q2 and Q4 into saturation, producing a low output.
Table 4-l summarizes all input and output conditions.
Incidentally, without diode D 1 in the circuit, Q3 would conduct slightly when the output is low. To prevent this, the diode is inserted; its voltage drop keeps the base-emitter
TABLE 4-1.
TWOINPUT
NAND GATE
A
B
0
0
0
y
1
0
0
Two quantities needed for our later discussions are power dissipation and propagation delay time. A standard TTL gate has_ a power dissipation ?f about ~mW. It may vary from this value because of signal levels, tolerances, etc., but on the average, it's 10 mW per gate.
The propagation delay time is the amount of time it takes for the output of a gate to change after the inputs have changed. The propagation delay time of a TTL gate is in the vicinity of 10 ns.
Device Numbers
By varying the design of Fig. 4-1 manufacturers can alter the number of inputs and the logic function. The multipleemitter inputs and the totem-pole outputs are still used, no matter what the design. (The only exception is an open collector, discussed later.)
Table 4-2 lists some of the 7400-series TTL gates. For instance, the 7400 is a chip with four 2-input NAND gates in one package. Similarly, the 7402 has four 2-input NOR gates, the 7404 has six inverters, and so on.
TABLE 4-2. STANDARD TTL
Device number
Description
7400
7402
7404
7408
7410
7411
7420
7421
7427
7430
7486
Quad 2-input NAND gates
Quad 2-input NOR gates
Hex inverter
Quad 2-input AND gates
Triple 3-input NAND gates
Triple 3-input AND gates
Dual 4-input NAND gates
Dual 4-input AND gates
Triple 3-input NOR gates
8-input NAND gate
Quad 2-input XOR gates
Chapter4
TTL Circuits
49
5400 Series
Any device in the 7400 series works over a temperature range of oo to 70°C and over a supply range of 4.75 to
5.25 V. This is adequate for commercial applications. The
5400 series, developed for the military applications, has the same logic functions as the 7400 series, except that it works over a temperature range of -55 to l25°C and over a supply range of 4.5 to 5.5 V. Although 5400-series devices can replace 7400-series devices, they are rarely used commercially because of their much higher cost.
High-Speed TTL
The cir~uit of Fig. 4-1 is called standard TTL. By decreasing the resistances a manufacturer can lower the internal time constants; this decreases the propagation delay time. The s_maller resistances, however, increase the power dissipation. This variation is known as high-speed TTL. Devices of this type are numbered 74HOO, 74H01, 74H02, and so on. A high-speed TTL gate has a power dissipation around
22 mW and a propagation delay time of approximately 6 ns. This virtually el_i~~~~?atl,lnttion delay.time, which means better switching speed. This variation is called Schottky
TTL; the devices are numbered 74SOO, 74S01, 74S02, and so forth.
Schottky TTL devices are very fast, capable of operating reliably at 100 MHz. The 74SOO has a power dissipation around 20 mW per gate and a propagation delay time of approximately 3 ns.
Low-Power Schottky TTL
By increasing internal resistances as well as using Schottky diodes manufacturers have come up with the best compromise between low power and high speed: low-power Schottky
TTL. Devices of this type are numbered 74LSOO, 74LS01,
74LS02, etc. A low-power Schottky gate has a power dissipation of around 2 mW and a propagation delay time of approximately 10 ns, as shown in Table 4-3.
Standard TTL and low-power Schottky TTL are the mainstays of the digital designer. In other words, of the five TTL types listed in Table 4-3, standard TTL and lowpower Schottky TTL have emerged as the favorites of the digital designers. You will see them used more than any other bipolar types.
Low-Power TTL
By increasing the internal resistances a manufacturer can reduce the power dissipation of TTL gates. Devices of this type are called low-power TTL and are numbered 74LOO
74L01, 74L02, etc. These devices are slower than standard
TTL because of the larger internal time constants. A lowpower TTL gate has a power dissipation of approximately
1 mW and a propagation delay time around 35 ns.
Schottky TTL
With standard TTL, high-speed TTL, and low-power TTL, the transistors go into saturation causing extra carriers to flood the base. If you try to switch this transistor from saturation to cutoff, you have to wait for the extra carriers to flow out of the base; the delay is known as the saturation delay time.
One way to reduce saturation delay time is with Schottky
TTL. The idea is to fabricate a Schottky diode along with each bipolar transistor of a TTL circuit, as shown in Fig.
4-2. Because the Schottky diode has a forward voltage of only 0.4 V, it prevents the transistor from saturating fully.
Fig. 4-2 Schottky diode prevents transistor saturation.
50
Digital Computer Electronics
4-3 TTL CHARACTERISTICS
7400-series devices are guaranteed to work reliably over a temperature range of 0 to 70°C and over a supply range of
4.75 to 5.25 V. In the discussion that follows, worst case means that the parameters (characteristics like maximum input current, minimum output voltage, and so on) are measured under the worst conditions of temperature and voltage-maximum temperature and minimum voltage for some parameters, minimum temperature and maximum voltage for others, or whatever combination produces the worst values.
Floating Inputs
When a TTL input is low or grounded, a current h
(conventional direction) exists in the emitter, as shown in
TABLE 4-3. TTL POWER-DELAY VALUES
Type
Power, mW Delay time, ns Low-power
Low-power Schottky
Standard
High-speed
Schottky
1
2
10
22
20
35
10
10
6
3
+5V--+---
+5V=e--+5
4kQ
v
+5V=e--4kQ
Open~
(high)~
low
Take the other extreme. Suppose V1 is 5 V in Fig. 4-4.
This is a high input; therefore, the output of the inverter is low. V1 can decrease all the way down to 2 V, and the output will still be low. Data sheets list this worst -case high input as
VIH = 2
Open
v
VEL = 0.8
---
(b)
(a)
VE to 0.8 V and still have a high output. The maximum low-level input voltage is designated VEL· Data sheets list this worst-case low input as
v
---
f
(c)
(d)
1(
In other words, any input voltage from 2 to 5 V is a high input for TTL devices.
Fig. 4-3 Open or floating input is the same as a high input.
Worst-Case Output Voltages
Fig. 4-3a. On the other hand, when a TTL input is high
(Fig. 4-3b), the emitter diode cuts off and the emitter current is approximately zero.
When a TTL input is floating (unconnected), as shown in Fig. 4-3c, no emitter current is possible. Therefore, a floating TTL input is equivalent to a high input. In other words, Fig. 4-3c produces the same output as Fig. 4-3b.
This is important to remember. In building circuits any floating TTL input will act like a high input.
Figure 4-3d emphasizes the point. The input is floating and is equivalent to a high input; therefore, the output of the inverter is low.
Ideally, 0 V is the low output, and 5 V is the high output.
We cannot attain these ideal values because of internal voltage drops. When the output is low in Fig. 4-4, Q4 is saturated and has a small voltage drop across it. With TTL devices, any voltage from 0 to 0.4 V is a low output.
When the output is high, Q3 acts like an emitter follower.
Because of the drop across Q3 , D 1 , and the 130-fl resistor, the output is less than 5 V. With TTL devices, a high output is between 2.4 and 3.9 V, depending on the supply voltage, temperature, and load.
This means that the worst-case output values are
VoL= 0.4 V
r-----.----.---o+5V
4kQ
1.6 kQ
130 [2
VoH = 2.4 V
Table 4-4 summarizes the worst-case values. Remember that they are valid over the temperature range (0 to 70°C) and supply range (4.75 to 5.25 V).
Compatibility
The values shown in Table 4-4 indicate that TTL devices are compatible. This means that the output of a TTL device can drive the input of another TTL device, as shown in
Fig. 4-5a. To be specific, Fig. 4-5b shows a low TTL output (0 to 0.4 V). This is low enough to drive the second
TTL device because any input less than 0.8 V is a low input. Fig. 4-4 TTL inverter.
TABLE 4-4. TTL STATES (WORST
CASE)
Worst-Case Input Voltages
Figure 4-4 shows a TTL inverter with an input voltage of
VE and an output voltage of V0 • When VE is 0 V (grounded), the output voltage is high. With TTL devices, we can raise
Low
High
Output, V
Input, V
0.4
2.4
0.8
Chapter 4
-
-~------------
2
TTL Circuits
51
------·-----------
direction shown. The charges flow from the emitter of Q 1
TTL
TTL device device
Va
"'
(a)
------4..._- +5
v
130Q
to the collector of Q4 • Because it is saturated, Q4 acts like a current sink; charges flow through it to ground like water flowing down a drain.
On the other hand, when a standard TTL output is high
(Fig. 4-5c), a reverse emitter current of 40 J.LA (worst case) exists in the direction shown. Charges flow from Q 3 to the emitter of Q 1 • In this case, Q 3 is acting like a source.
Data sheets lists the worst-case input currents as
+5V--+---
IIL = -1.6 rnA
IIH
= 40 J.LA
The minus sign indicates that the current is out of the device; plus means the current is into the device. All data sheets use this convention.
0 to 0.4 V
Less than 0.8 V is low input
Standard Loading
A TTL device can source current (high output) or it can sink current (low output). Data sheets of standard TTL devices indicate that any 7400-series device can sink up to
16 rnA, designated as
(b)
---+--+5V
130Q
IoL = 16 rnA
+5V--+--
and can source up to 400 J.LA, designated loH =
-400 J.LA
2.4 to 3.9 V
More than 2 V is high input
(c)
Fig. 4-5 Sourcing and sinking current.
Similarly, Fig. 4-5c shows a high TTL output (2.4 to
3.9 V). This is more than enough to drive the second TTL because any input greater than 2 V is a high input.
Noise Margin
In the worst case, there is a margin ofO..Jl-\'. between the driver and the load in Fig. 4-5b and c. This difference, called the noise margin, represents protection against noise.
In other words, the connecting wire between a TTL driver and a TTL load may pick up stray noise voltages. As long as these induced voltages are less than 0.4 V, we get no false triggering of the TTL load.
Sourcing and Sinking
When a standard TTL output is low (Fig. 4-5b), an emitter current of approximately 1.6 rnA (worst case) exists in the
52
Digital Computer Electronics
(Again, a minus sign means that the current is out of the device and a plus sign means that it's into the device.)
A single TTL load has a low-level input current of 1.6 rnA (Fig., 4-5b) and a high-level input current of 40 J.LA
(Fig. 4-5c). Since the maximum output currents are 10 times as large, we can connect up to 10 TTL emitters to any TTL output.
Figure 4-6a illustrates a low output. Here you see the
TTL driver sinking 16 rnA, the sum of 10 TTL load currents. In this state, the output voltage is guaranteed to be 0.4 V or less. If you try connecting more than 10 emitters, the output voltage may rise above 0.4 V.
Figure 4-6b shows a high output with the driver sourcing
400 J.LA for 10 TTL loads of 40 J.LA each. For this maximum loading, the output voltage is guaranteed to be 2.4 V or more under worst-case conditions.
Loading Rules
The maximum nnmber of TTL emitters that can be reliably driven under worst-case conditions is called the fanout.
With standard TTL, the fanout is 10, as shown in Fig.
4-6. Sometimes, we may want to use a standard TTL device to drive low-power Schottky devices. In this case, the fanout increases because low-power Schottky devices have less input current.
1.6mA
the right. Pick the driver, pick the load, and read the fanout at the intersection of the two. For instance, the fanout of a standard device (74) driving low-power Schottky devices
(74LS) is 20. As -another example, the fanout of a lowpower device (74L) driving high-speed devices (74H) is only 1.
TTL device 1
1.6mA
16mA
TTL
TTL
device
2
device
I
i
4-4 TTL OVERVIEW
I
I
I
1.6mA
Let's take a look at the logic functions available in the
7400 series. This overview will give you an idea of the variety of gates and circuits found in the TTL family. As guide, Appendix 3 lists some of the 7400-series devices.
You will find it useful when looking for a device number or logic function.
TTL device 10
(a)
40
J.LA
TTL device 1
400 pA
40pA
TTL
TTL
device
2
device
I
(a}
(b)
I
I
I
I
I
40pA
TTL device 10
,,
(b)
Fig. 4-6 Fanout of standard TTL devices: (a) low output; (b) high output.
(c)
By examining data sheets for the different TTL types we can calculate the fanout for all possible combinations. Table
4-5 summarizes these fan outs, which may be useful if you ever have to mix TTL types.
Read Table 4-5 as follows. The series numbers have been abbreviated; 74 stands for 7400 series, 74H for 74HOO series, and so forth. Drivers are on the left and loads on
TABLE 4-5. FANOUTS
Fig. 4-7 Three, four, and eight inputs.
NAND Gates
To begin with, the NAND gate is the backbone of the entire series. All devices in the 7400 series are derived from the
2-input NAND gate shown in Fig. 4-1. To produce 3-, 4-, and 8-input NAND gates the manufacturer uses 3-, 4-, and
8-emitter transistors, as shown in Fig. 4-7. Because they are so basic, NAND gates are the least expensive devices in the 7400 series.
TTL load
TTL driver 74
74H
74L
74-.5_
74LS
74
74H
74L
74S
74LS
lO
12
2
12
5
8 lO 40
50
20 lOO 40
8 lO 1 lO 4
20
25
lO
50
20
10
4
NOR Gates
To get other logic functions the manufacturer modifies the basic NAND-gate design. For instance, Fig. 4-8 shows a 2input NOR gate. Q1 , Q2 , Q3 , and Q4 are the same as in the basic design. Q 5 and Q 6 have been added to produce oRing.
Notice that Q 2 and Q 6 are in parallel, the key to the oRing followed by inversion to get NORing.
Chapter 4
1TL Circuits
53
----------------------------
r-------.-------------~------~---+5V
4kQ
------
The input currents are the same as those of a standard NAND gate, but the output currents are 3 times as high, which means that the 7437 can drive heavier loads.
Appendix 3 includes several other buffer-drivers.
a
A
01
y
8 _________..r
Os
Fig. 4-8 TTL
NOR
~
,y ' y,
J~f,
-
gate.
-
..-I<J--e d (a)
I
I
(b)
Fig. 4-9 Seven-segment display.
When A and B are both low, Q 1 and Q 5 are saturated; this cuts off Q 2 and Q6 . Then Q 3 acts like an emitter follower and we get a high output.
If A orB or both are high, Q 1 or Q 5 or both are cut off, forcing Q2 or Q6 or both to tum on. When this happens,
Q4 saturates and pulls the output down to a low voltage.
With more transistors, manufacturers can produce 3- and
4-input NOR gates. (A TTL 8-input NOR gate is not available.)
AND
and
OR
Gates
To produce the AND function, another common-emitter stage is inserted before the totem-pole output of the basic
NAND gate design. The extra inversion converts the NAND gate to an AND gate. Similarly, another CE stage can be inserted before the totem-pole output of Fig. 4-8; this converts the NOR gate to an OR gate.
Buffer-Drivers
A buffer is a device that isolates two other devices.
Typically, a buffer has a high input impedance and a low output impedance. In terms of digital ICs, this means a low input current and a high output current.
Since the output current of a standard TTL gate can be
10 times the input current, a basic gate does a certain amount of buffering (isolating). But it's only when the manufacturer optimizes the design for high output currents that we call a device a buffer or driver.
As an example, the 7437 is a quad 2-input NAND buffer, meaning four 2-input NAND gates optimized to get high output currents. Each gate has the following worst-case values of input and output currents: l1L = -1.6 rnA loL = 48 rnA
54
1/H
=
loH =
Digital Computer Electronics
40 f.LA
-1.2 rnA
Encoders and Decoders
A number of TTL chips are available for encoding and decoding data. For instance, the 74147 is a decimal-toBCD encoder. It has 10 input lines (decimal) and 4 output lines (BCD). As another example, the 74154 is a 1-of-16 decoder. It has 4 input lines (binary) and 16 output lines
(hexadecimal).
Seven-segment decoders (7446, 7447, etc.) are useful for decimal displays. They convert a BCD nibble into an output that can drive a seven-segment display. Figure 4-9a illustrates the idea behind a seven-segment LED display. It has seven separate LEDs that allow you to display any digit between 0 and 9. To display a 7, the decoder will tum on
LEDs a, b, and c (Fig. 4-9b).
Seven-segment displays are not limited to decimal numbers. For instance, in some microprocessor trainers, sevensegment displays are used to indicate hexadecimal digits.
Digits A, C, E, and F are displayed in uppercase form; digit B is shown as a lowercase b (LEDs c, d, e, f, g); and digit D as a lowercase d (LEDs b, c, d, e, g).
Schmitt Triggers
When a computer is running, the outputs of gates are rapidly switching from one state to another. If you look at these signals with an oscilloscope, you see signals that ideally resemble rectangular waves like Fig. 4-10a.
When digital signals are transmitted and later received, they are often c"orrupted by noise, attenuation, or other factors and may wind up looking like the ragged waveform shown in Fig. 4-lOb. If you try to use these nonrectangular signals to drive a gate or other digital device, you get unreliable operation.
This is where the Schmitt trigger comes in. It designed to clean up ragged looking pulses, producing almost vertical
(discussed in the next section), latches and flip-flops (Chap.
7), registers and counters (Chap. 8), and memories (Chap.
9).
(a)
4-5 AND·OR•INVERT GATES
Figure 4-12a shows an AND-OR circuit. Figure 4-12b shows the De Morgan equivalent circuit, a NAND-NAND network.
In either case, the boolean equation is
(b)
_n_-
Schmitt trigger (4-1)
Y = AB +CD
Since NAND gates are the preferred TTL gates, we would build the circuit of Fig. 4-12b. NAND-NAND circuits like this are important because with them you can build any desired logic circuit (discussed in Chap. 5).
(c)
Fig. 4-10 Schmitt trigger produces rectangular output.
TTL Devices
Is there any TTL device with the output given by Eq. 4-1?
Yes, there are some AND-OR gates but they are not easily derived from the basic NAND-gate design. The gate that is easy to derive and comes close to having an expression like
Eq. 4-1 is the AND-OR-INVERT gate shown in Fig. 4-12c.
In other words, a variety of circuits like this are available on chips. Because of the inversion, the output has an equation of
(a)
(4-2)
Y = AB +CD
A
~
~
Fig. 4-11 (a) Hex Schmitt-trigger inverters; (b) 4-input
Schmitt trigger; (c) 2-input NAND Schmitt trigger.
8
NAND
c
D
(a)
transitions between the low and high state, and vice versa
(Fig. 4-IOc). In other words, the Schmitt trigger produces a rectangular output, regardless of the input waveform.
The 7414 is a hex Schmitt-trigger inverter, meaning six
Schmitt-trigger inverters in one package like Fig. 4-11a.
Notice the hysteresis symbol inside each inverter; it designates the Schmitt-trigger function.
Two other TTL Schmitt triggers are available. The 7413 is a dual4-input NAND Schmitt trigger, two Schmitt-trigger gates like Fig. 4-llb. The 74132 is a quad 2-input NAND
Schmitt trigger, four Schmitt-trigger gates like Fig. 4-11c.
A
8 y c
D
(b)
A
8
c
D
Other Devices
(c)
The 7400 series also includes a number of other devices that you will find useful, such as AND-OR-INVERT gates
Fig. 4-12 (a) AND-OR circuit; (b)
OR-INVERT circuit.
NAND-NAND
Chapter 4
circuit; (c)
TTL Circuits
AND-
55
4k0
1.6 kO
1300
I,
A
y
8
c-----....r
(a)
D ---------'
Fig. 4-13
AND-OR-INVERT
schematic diagram.
Figure 4-13 shows the schematic diagram of a TTL ANDOR-INVERT gate. Q,, Q 2 , Q 3 , and Q 4 form the basic 2-input
NAND gate of the 7400 series. By adding Q 5 and Q6 we convert the basic NAND gate to an AND-OR-INVERT gate.
Q 1 and Q5 act like 2-input AND gates; Q 2 and Q 6 produce
ORing and inversion. Because of this, the circuit is logically equivalent to Fig. 4-12c.
In Table 4-6, listing the AND-OR-INVERT gates available in the 7400 series, 2-wide means two AND gates across, 4wide means four AND gates across, and so on. For instance, the 7454 is a 2-input 4-wide AND-OR-INVERT gate like Fig.
4-14a; each AND gate has two inputs (2-input) and there are four AND gates (4-wide). Figure 4-14b shows the 7464; it is a 2-2-3-4-input 4-wide AND-OR-INVERT gate.
When we want the output given by Eq. 4-1, we can connect the output of a 2-input 2-wide AND-OR-INVERT gate to another inverter. This cancels out the internal inversion, giving us the equivalent of an AND-OR circuit (Fig. 4-12a) or a NAND-NAND network (Fig. 4-12b).
Expandable
AND-OR-INVERT
Gates
The widest AND-OR-INVERT gate available in the 7400 series is 4-wide. What do we do when we need a 6- or 8-wide circuit? One solution is to use an expandable AND-ORINVERT gate.
TABLE 4-6. AND-OR-INVERT GATES
56
Device
Description
7451
7454
7459
7464
Dual 2-input 2-wide
2-input 4-wide
Dual 2-3 input 2-wide
2-2-3-4 input 4-wide
Digital Computer Electronics
(b)
Fig. 4-14 Examples of AND-OR-INVERT circuits.
Figure 4-15a shows the schematic diagram of an expandable AND-OR-INVERT gate. The only difference between this and the preceding AND-OR-INVERT gate (Fig. 4-13) is collector and emitter tie points brought outside the package.
Since Q 2 and Q 6 are the key to the ORing operation, we are being given access to the internal ORing function. By connecting other gates to these new inputs we can expand the width of the AND-OR-INVERT gate.
Figure 4-15b shows the logic symbol for an expandable
AND-OR-INVERT gate. The arrow input represents the emitter, and the bubble stands for the collector. Table 4-7 lists the expandable AND-OR-INVERT gates in the 7400 series.
Expanders
What do we connect to the collector and emitter inputs of an expandable gate? The output of an expander like Fig.
4-16a. The input transistor acts like a 4-input AND gate.
The output transistor is a phase splitter; it produces two
TABLE 4-7. EXPANDABLE AND-OR·
INVERT GATES
Device
7450
7453
7455
Description
Dual 2-input 2-wide
2-input 4-wide
4-input 2-wide
Collector
+5
4kS1
v
1.6 kQ
A
8
y
c
A
D
y
8
c
Collector
06
Emitter
D
Emitter
(a)
(b)
Fig. 4-15 (a) Expandable AND-OR-INVERT gate;
+5
(b)
logic symbol.
v
4kS1
Collector
~Collector
~Emitter
Emitter
(b)
(a)
y
y
y
(c)
Fig. 4-16 (a) Expander; (b) symbol for expander; (c) expander driving expandable AND-OR-INVERT gate; (d) AND-OR-INVERT circuit; (e) expandable AND-OR-INVERT with two expanders.
output signals, one in phase (emitter) and the other inverted
(collector). Figure 4-16b shows the symbol of a 4-input expander. Visualize the outputs of Fig. 4-16a connected to the collector and emitter inputs of Fig. 4-15a. Then Q8 is in parallel with Q 2 and Q6 • Figure 4-16c shows the logic circuit. This means that the expander outputs are being oRed with the signals of the AND-OR-INVERT gate. In other
(d)
(e)
words, Fig. 4-l6c is equivalent to the AND-OR-INVERT circuit of Fig. 4-16d.
We can connect more expanders. Figure 4-16e shows two expanders driving the expandable gate. Now we have a 2-2-4-4-input 4-wide AND-OR-INVERT circuit.
The 7460 is a dual 4-input expander. The 7450, a dual expandable AND-OR-INVERT gate, is designed for use with up to four 7460 expanders. This means that we can add two more expanders in Fig. 4-16e to get a 2-2-4-4-4-4input 6-wide AND-OR-INVERT circuit.
Chapter 4
TTL Circuits
57
4-6 OPEN-COLLECTOR GATES
Instead of a totem-pole output, some TTL devices have an open-collector output. This means they use only the lower transistor of a totem-pole pair. Figure 4-17 a shows a 2input NAND gate with an open-collector output. Because the collector of Q 4 is open, a gate like this won't work properly until you connect an external pull-up resistor, shown in Fig. 4-17b.
Data Selection
Figure 4-18 shows a 16-to-1 multiplexer, also called a data selector. The input data bits are D 0 to D 15 • Only one of these is transmitted to the output. Control word ABCD determines which data bit is passed to the output. For instance, when
ABCD
=
0000
the upper AND gate is enabled but all other AND gates are disabled. Therefore, data bit D0 is transmitted to the output, giving y =Do
If the control word is changed to
ABCD
=
1111
the bottom gate is enabled and all other gates are disabled.
In this case,
(a)
Boolean Function Generator
+5
v
Pull-up resistor Digital design often starts with a truth table. The problem then is to come up with an equivalent logic circuit.
Multiplexers give us a simple way to transform a truth table into an equivalent logic circuit. The idea is to use input data bits that are equal to the desired output bits of the truth table.
For example, look at the truth table of Table 4-8. When the input word ABCD is 0000, the output is 0; when ABCD
TABLE 4-8
(b)
Fig. 4-17 Open-collector TTL: (a) circuit; (b) with pull-up resistor.
The outputs of open-collector gates can be wired together and connected to a common pull-up resistor. This is known as WIRE-OR. The big disadvantage of open-collector gates is their slow switching speed.
Open-collector gates are virtually obsolete because a new device called the three-state switch appeared in the early
1970s. Section 8-8 discusses three-state switches in detail.
4-7 MULTIPLEXERS
Multiplex means "many into one." A multiplexer is a circuit with many inputs but only one output. By applying control signals we can steer any input to the output.
58
Digital Computer Electronics
A
B
c
D
y
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
0
1
0
0
0
0
0
I
0
1
0
I
0
0
0
0
0
0
0
0
1
0
A
8
cc
~ ~ ~ ~
-r\
.
o,
'
L-1
'
:~"""'.
i.-1
\
J
'
L....l
'
-L--1
J
J
I
y
I
Dg
o,,
J
-r---'\
i.-1
~
i.-1
'
Fig. 4-18 A 16-to-1 multiplexer.
Chapter 4
TTL Circuits
59
-----------------····---
A
8
c
D
Universal Logic Circuit
The 74150 is a 16-to-1 multiplexer. This TTL device is a universal logic circuit because you can use it to get the hardware equivalent of any four-variable truth table. In other words, by changing the input data bits the same IC can be made to generate thousands of different truth tables.
0
0
0
0
0
1
0
0
0
0
0
0
1
0
16 to 1 data selector/
y
Multiplexing Words
Figure 4-20 illustrates a word multiplexer that has two input words and one output word. The input word on the left is
L3 L2L,L0 and the one on the right is R 3R 2R 1R0 . The control signal labeled RIGHT selects the input word that will be transmitted to the output. When RIGHT is low, the four
NAND gates on the left are activated; therefore,
Fig. 4-19 Generating a boolean function.
= 0001 , the output is 1; when ABCD = 0010, the output is 0; and so on. Figure 4-19 shows how to set up a multiplexer with the foregoing truth table. When ABCD
0000, data bit 0 is steered to the output; when ABCD
= 0001, data bit 1 is steered to the output; when ABCD
= 0010, data bit 0 is steered to the output; and so forth.
As a result, the truth table of this circuit is the same as
Table 4-8.
When RIGHT is high,
The 74157 is TTL multiplexer with an equivalent circuit like Fig. 4-20. Appendix 3 lists other multiplexers available in the 7400 series.
OUT
Fig. 4-20 Nibble multiplexer.
GLOSSARY bipolar Having two types of charge carriers: free electrons and holes. chip A small piece of semiconductor material. Sometimes, chip refers an IC device including its pins.
60
Digital Computer Electronics
fanout The maximum number of TTL loads that a TTL device can drive reliably over the specified temperature range. low-power Schottky TTL A modification of standard TTL
in which larger resistances and Schottky diodes are used.
The increased resistances decrease the power dissipation, and the Schottky diodes increase the speed. multiplexer A circuit with many inputs but only one output. Control signals select which input reaches the output. noise margin The amount of noise voltage that causes unreliable operation. With TTL it is 0.4 V. As long as noise voltages induced on connecting lines are less than
0.4 V, the TTL devices will work reliably. saturation delay time The time delay encountered when a transistor tries to come out of the saturation region. When the base drive switches from high to low, a transistor cannot instantaneously come out of saturation; extra carriers that flooded the base region must first flow out of the base.
Schmitt trigger A digital circuit that produces a rectangular output from any input large enough to drive the Schmitt trigger. The input waveform may be sinusoidal, triangular, distorted, and so on. The output is always rectangular. sink A place where something is absorbed. When saturated, the lower transistor in a totem-pole output acts like a current sink because conventional charges flow through the transistor to ground. source A place where something originates. The upper transistor of a totem-pole output acts like a source because charges flow out of its emitter into the load. standard TTL The initial TTL design with resistance values that produce a power dissipation of 10 mW per gate and a propagation delay time of 10 ns.
SELF-TESTING REVIEW
Read each of the following and provide the missing words.
Answers appear at the beginning of the next question.
7.
1.
Small-scale integration, abbreviated
, refers to fewer than 12 gates on the same chip.
Medium-scale integration (MSI) means 12 to 100 gates per chip. And large-scale integration (LSI) refers to more than gates per chip.
2. (SSI, /00) The two basic technologies for digital
ICs are bipolar and MOS. Bipolar technology is preferred for and , whereas
MOS technology is better suited to LSI. The reason
MOS dominates the LSI field is that more _ _ __ can be fabricated on the same chip area.
3. (SS/, MSI, MOSFETs) Some of the bipolar families include DTL, TTL, and ECL. has become the most widely used bipolar family. _ __ is the fastest logic family; it's used in high-speed applications. 4. (TTL, ECL) Some of the MOS families are PMOS, dominates the LSI
NMOS, and CMOS. field, and is used extensively where lowest power consumption is necessary.
5. (NMOS, CMOS) The 7400 series, also called standard TTL, contains a variety of SSI and _ _ __ chips that allow us to build all kinds of digital circuits and systems. Standard TTL has a multipleemitter input transistor and a _____ output.
The totem-pole output produces a low output impedance in either state.
6. (MSI, totem-pole) Besides standard TTL, there is high-speed TTL, low-power TTL, Schottky TTL, and low-power
TTL. Standard TTL and low-power TTL have become the favorites of digital designers, used more than any other bipolar families.
8.
9.
10.
11.
(Schottky, Schottky) 7400-series devices are guaranteed to work reliably over a range of 0 to 70°C and over a voltage range of 4.75 to 5.25 V.
A floating TTL input has the same effect as a
_ _ _ _ input.
(temperature, high) A
TTL device can sink up to 16 rnA and can source up to 400 fLA.
The maximum number of TTL loads a TTL device can drive is called the
. With standard
TTL, the fanout equals _ _ __
(standard, fanout, 10) A buffer is a device that isolates other devices. Typically, a buffer has a high input impedance and a output impedance. In terms of digital ICs, this means a _ _ __ input current and a high output current capability.
(low, low) A Schmitt trigger is a digital circuit that produces a output regardless of the input waveform. It is used to clean up ragged looking pulses that have been distorted during transmission from one place to another.
(rectangular) A multiplexer is a circuit with many inputs but only one output. It is also called a data selector because data can be steered from one of the inputs to the output. A 74150 is a 16-to-1 multiplexer. With this TTL device you can implement the logic circuit for any four-variable truth table.
Chapter 4
TTL Circuits
61
PROBLEMS
+5
v
a
~
,y ' y,
130Q
03
J~f,
o, v, ~
Va
I
I
d
(a)
04
(b)
Fig. 4-22
Fig. 4-21
4-1.
4-2.
4-3.
4-4.
62
-
-
In Fig. 4-21 a grounded input means that almost the entire supply voltage appears across the 4-kll resistor. Allowing 0.7 V for the emitter-base voltage of Q 1 , how much input emitter current is there with a grounded input? The supply voltage can be as high as 5.25 V and the 4-kll resistance can be a low as 3.28 kll. What is the input emitter current in this case?
What is the fanout of a 74SOO device when it drives low-power TTL loads?
What is the fanout of a low-power Schottky device driving standard TTL devices?
Section 4-4 gave the input and output currents for a
7437 buffer. What is the fanout of a 7437 when it drives standard TTL loads?
Digital Computer Electronics
4-5.
4-6.
4-7.
4-8.
4-9.
4-10.
A seven-segment decoder is driving a LED display like Fig. 4-22a. Which LEDs are on when digit 8 appears? Which LEDs are on when digit 4 appears?
Section 4-7 described the 74150, a 16-to-1 multiplexer. Refer to Fig. 4-23 and indicate the values the D 0 to D 15 inputs of a 74150 should have to reproduce the following truth table: The output is high when ABCD = 0000, 0100, 0111, 1100, and 1111; the output is low for all other inputs.
What is propagation delay?
Why are 5400 series devices not normally used in commercial applications?
What do Schottky devices virtually eliminate which makes their high switching speeds possible?
What is the noise margin of TTL devices?
A
8
~ ~
c
D
7 l7
1\
Do
'
_.)
01
02
03
-r---\
04
05
-!...-1
'
-L-J
\
06
-L-J
07
\
Dg
-L-J
l
I
y
j
Dg
1"'\
010
-L-1
/
011
j
012
013
014
-L-1
'
_J
015
Fig. 4-23
Chapter 4
TTL Circuits
63
BOOLEAN ALGEBRA AND
KARNAUGH MAPS
This chapter discusses boolean algebra and Karnaugh maps, topics needed by the digital designer. Digital design usually begins by specifying a desired output with a truth table.
The question then is how to come up with a logic circuit that has the same truth table. Boolean algebra and Karnaugh maps are the tools used to transform a truth table into a practical logic circuit.
;=D-y
~=D-y
(a)
;=o--y :=o---y
(b)
5-l BOOLEAN RELATIONS
What follows is a discussion of basic relations in boolean algebra. Many of these relations are the same as in ordinary algebra, which makes remembering them easy.
Given a 2-input OR gate, you can transpose the input signals without changing the output (see Fig. 5-l a). In boolean terms A+B=B+A
64
+
(B
+
C) = (A
(d)
8
A
y
c
(e)
Fig. S-1 Commutative, associative, and distributive laws.
(5-2)
BA
The foregoing relations are called commutative laws.
The next group of rules are called the associative laws.
The associative law for ORing is
A
~~y
(5-1)
Similarly, you can transpose the input signals to a 2-input
AND gate without affecting the output (Fig. 5-lb). The boolean equivalent of this is
=
(c)
~=U-=0-y
Commutative, Associative, and
Distributive Laws
AB
;~y
~D=D--y
+
B)
+
C
(5-3)
Figure 5-lc illustrates this rule. The idea is that how you group variables in an ORing operation has no effect on the output. For either gate in Fig. 5-l c the output is
Y=A+B+C
Similarly, the associative law for ANDing is
A(BC) = (AB)C
Another boolean relation is
A+A=A
(5-4)
(5-7)
which is illustrated in Fig. 5-2b. You can see what happens.
If A is 0, the output is 0; if A is 1, the output is 1; therefore, a variable ORed with itself equals the variable.
Figure 5-2c shows the next boolean rule:
Figure 5-1d illustrates this rule. How you group variables in ANDing operations has no effect on the output. For either gate of Fig. 5-1d the output is
Y =ABC
A
+
1 = 1
(5-8)
The distributive law states that
A(B
+
C) = AB
+
AC
In a nutshell, if one input to an OR gate is 1, the output is
1 regardless of the other input.
Finally, we have
(5-5)
This is easy to remember because it's identical to ordinary algebra. Figure 5-1e shows the meaning in terms of gates.
OR
A+A=
(5-9)
shown in Fig. 5-2d. In this case, a variable ORed with its complement equals 1.
Operations
The next four boolean relations are about OR operations.
Here is the first:
A+O=A
AND
The first AND relation to know about is
(5-6)
A· 1 =A
This says that a variable ORed with 0 equals the variable.
For better grasp of this idea, look at Fig. 5-2a. (The solid arrow stands for "implies.") The two cases on the left imply the case on the right. In other words, if the variable is 0, the output is 0 (left gate); if the variable is 1, the output is 1 (middle gate); therefore, a variable ORed with
0 equals the variable (right gate).
~=D-o
and
Operations
(5-10)
illustrated in Fig. 5-3a. If A is 0, the output is 0; if A is 1, the output is 1; therefore, a variable ANDed with 1 equals the variable.
Another relation is
A· A= A
~=D--1
(5-11)
=> :=D-A
(a)
~=D-o
and
:=D--1 =>
~=D-A
(b)
~=D--1
and
:=D--1 =>
~=D-1
(c)
~=D--1
and
~=D--1
=> ;=D--1
(d)
Fig. 5-2
OR
relations.
Chapter 5
Boolean Algebra and Kamaugh Maps
65
~=D-o
and
:=o---1
:=o-A
:::>
(a)
~=D-o
and
:=0---1 => :=0---A
(b)
:=D-o
and
~=D-o
:=o---0
=>
(c)
~=D-o
and
~=D-o
=> ;=Q-o
(d)
Fig. 5-3
AND
relations.
shown in Fig. 5-3b. In this case, a variable ANDed with itself equals the variable.
Figure 5-3c illustrates this relation
A· 0
=
0
(5-12)
The rule is clear. If one input to an AND gate is 0, the output is 0 regardless of the other input.
The last AND rule is
Duality Theorem
We state the duality theorem without proof. Starting with a boolean relation, you can derive another boolean relation by 1.
2.
3.
Changing each OR sign to an AND sign
Changing each AND sign to an OR sign
Complementing each 0 and I
For instance, Eq. 5-6 says that
A ·A= 0
(5-13)
A+O=A
As shown in Fig. 5-3d, a variable ANDed with its complement produces a 0 output.
The dual relation is
A· I= A
Double Inversion and De Morgan's Theorems
The double-inversion rule is
A=A
(5-14)
which says that the double complement of a variable equals the variable. Finally, there are the De Morgan theorems discussed in Chap. 3:
A+ B = AB
AB=A+B
(5-15)
(5-16)
You should memorize Eqs. 5-1 to 5-16 because they are used frequently in design work.
66
Digital Computer Electronics
This is obtained by changing the OR sign to an AND sign, and by complementing the 0 to get a 1.
The duality theorem is useful because it sometimes produces a new boolean relation. For example, Eq. 5-5 states that
A(B
By changing each relation A
+
OR
+ BC
C) = AB
+ AC
and AND operation we get the dual
= (A
+ B)(A +
C)
This is a new boolean relation, not previously discussed.
(If you want to prove it, construct the truth table for the
left and right members of the equation. The two truth tables will be identical.)
TABLE 5-l. TWO VARIABLES
A B
Fundamental product
Summary
0 0
For future reference, here are some boolean relations and their duals:
0
AB
AB
AB
AB
AB = BA
A+B=B+A
A
+
(B
A(B
+
+
C) = (A
C) =
AB
+
+
B)
+
C
AC
A+O=A
A + 1 = 1
A+A=A
A+A=1
A=A
A+ B = AB
A+AB=A
A+AB=A+B
A(BC) = (AB)C
A+ BC =
(A + B)(A + C)
A· 1 =A
A· 0 = 0
AA =A
Ali= o
A=A
AB=A+B
A(A +B) =A
A (A+ B) = AB
5-2 SUM-OF-PRODUCTS METHOD
Digital design often starts by constructing a truth table with a desired output (0 or 1) for each input condition. Once you have this truth table, you transform it into an equivalent logic circuit. This section discusses the sum-of-products method, a way of deriving a logic circuit from a truth table.
A"=D--_
A8
8
(a)
(b)
A=D---
_
8
0
A8
(c)
(d)
Fig. 5-4 Fundamental products.
Fundamental Products
Figure 5-4 shows the four possible ways to AND two input signals and their complements. In Fig. 5-4a the inputs are
A and B. Therefore, the output is
Y=AB
The output is high only when A = 0 and B = 0.
Figure 5-4b shows another possibility. Here the inputs are A and B; so the output is
In this case, the output is 1 only ~hen A = 0 and B
In Fig. 5-4c the inputs are A and B. The output
1.
Y = AB
is high only when A = 1 and B = 0. Finally, in Fig.
5-4d the inputs are A and B. The output y = AB
is 1 only when A = 1 and B = 1.
Table 5-1 summarizes the four possible ways to AND two signals in complemented or uncomplemented form. The logical productsAB, AB, Aii, andAB are called fundamental products because each produces ~_!ligh output for its corresponding input. For instance, AB is a 1 when A is 0 and B is 0, AB is a 1 when A is 0 and B is 1, and so forth.
Three Variables
A similar idea applies to three signals in complemented and uncomplemented form. Given A, B, C, and t~:~_eE"5o~£le ments, there are eight fundamental products: ABC, ABC,
ABC, ABC, ABC, ABC, ABC, and ABC. Table 5-2 lists each input possibility and its fundamental product. Again notice this property: each fundamental product is high for the corresponding input. This means that ABC is a 1 when
A is 0, B is 0, and C is 0; ABC is a 1 when A is 0, B is
0, and C is 1; and so on.
TABLE 5-2. THREE VARIABLES
A B
c
Fundamental product
0
0
0
ABC
ABC
ABC
ABC
ABC
ABC
ABC
ABC
0
0
0
0
1
0
0
Y= AB
Chapter 5
0
1
0
1
0
Boolean Algebra and Kamaugh Maps
67
Four Variables
TABLE 5-4
TABLE 5-3
When there are 4 input variables, there are 16 possible input conditions, 0000 to 1111. The corresponding fundamental products are from ABCD through ABCD. Here is a quick way to find the fundamental product for any input condition. Whenever the input variable is 0, the same variable is complemented in the fundamental product. For instance, if the input condition is 0110, the fundamental product is ABCD. Similarly, if the input is 0100, the fundamental product is ABCD.
A
B
c
y
A
B
c
D
y
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1 ~ABC
1
1
0
0
0
0
0
1
0
1 ~ABC
1 ~ABC
1 ~ABC
Deriving a Logic Circuit
To get from a truth table to an equivalent logic circuit OR the fundamental products for each input condition that produces a high output. For example, suppose you have a truth table like Table 5-3. The fundamental products are listed for each high output. By ORing these products you get the boolean equation
Y = ABC
+ ABC + ABC + ABC
ABCD
+ ABCD + ABCD
-
A
8
8
0
0
0
1
0
1
1
0
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
0
0
0
0
-
AA88CCDD
y
Fig. 5-6
(5-18)
This ~~_ation implies that three AND gates are driving an
OR gate. The first AND gat~ has inputs of A, B, C, and D; the second has inputs of A, B, C, and D; the third has
A
1
0
0
0
-
=
1
0
0
(5-17)
This e.quati_<:>n implies four AND gates driving an OR gate.
The first AND gate has in~ts of A, B, and C; the second
AND gate has inputs of A, B, and C; the third AND gate has inputs of A, B, and C; the fourth AND gate has inputs of
A, B, and C. Figure 5-5 shows the corresponding logic circuit. This AND-OR circuit has the same truth table as
Table 5-3.
As another example of the sum-of-products method, look at Table 5-4. Find each output 1 and write its fundamental p~~uct. The resulting products are ABCD, ABCD, and
AB CD. This means that the boolean e_guatiQ!! is
Y
0
1
c c
inputs of A, B, C, and D. Figure 5-6 is the equivalent logic circuit. The sum-of-products method always works. You OR the fundamental products of each high output in the truth table.
This giv\':s an equation which you can transform into ari
AND-OR network that is the circuit equivalent of the truth table. 5-3 ALGEBRAIC SIMPLIFICATION y Fig. 5-5 Sum-of-products circuit.
68
Digital Computer Electronics
After obtaining a sum-of-products equation as described in the preceding section, the thing to do is to simplify the circuit if possible. One way to do this is with boolean algebra. Here is the approach. Starting with the boolean equation for the sum-of-products circuit, you try to rearrange and simplify the equation as much as possible using the boolean rules of Sec. 5-1. The simplified boolean equation means a simpler logic circuit. This section will give you examples. A
AA88CCDD
A
8
8
y y (a)
-
A
(a)
A
A
8
8
c
C
D
i5
A
-
8
8
Is==n-Jy
tI tt
c_;
(b)
y
A
A
8
8
~t
I -+---+--1
I
(b)
- Y
Fig. S-7
(c)
Fig. S-8
Gate Leads
A preliminary guide for comparing the simplicity of one logic circuit with another is to count the number of input gate leads; the circuit with fewer input gate leads is usually easier to build. For instance, the AND-OR circuit of Fig.
5-7 a has a total of 15 input gate leads (4 on each AND gate and 3 on the OR gate). The AND-OR circuit of Fig. 5-7b, on the other hand, has a total of 9 input gate leads. The
AND-OR circuit of Fig. 5-7b is simpler than the AND-OR circuit of Fig. 5-7a because it has fewer input gate leads.
A bus is a group of wires carrying digital signals. The
8-bit bus of Fig. 5-]_a !a~mits v~iables A, B, C, D and their complements A, B, C, and D. In the typical microcomputer, the microprocessor, memory, and I/0 units exchange data by means of buses.
Factoring to Simplify
One way to reduce the number of input gate leads is to factor the boolean equation if possible. For instance, the boolean equation
Y=AB+AB
(5-19)
has the equivalent logic circuit shown in Fig. 5-8a. This circuit has six input gate leads. By factoring Eq. 5-19 we get Y = A(B
+
The equivalent logic circuit for this is shown in Fig. 5-8b; it has only four input gate leads.
Recall that a variable ORed with its complement always equals 1; therefore,
Y = A(B
+
B) = A · 1 = A
To get this output, all we need is a connecting wire from the input to the output, as shown in Fig. 5-8c. In other words, we don't need any gates at all.
Another Example
Here is another example of how factoring can simplify a boolean equation and its corresponding logic circuit. Suppose we are given
Y
=
AB
+
AC
+
BD
+
CD
(5-20)
In this equation, two variables at a time are being ANDed.
The logical products are then ORed to get the final output.
Figure 5-9a shows the corresponding logic circuit. It has
12 input gate leads.
We can factor and rearrange Eq. 5-20 as
B)
Y = A(B
Chapter 5
+
C)
+
D(B
+
C)
Boolean Algebra and Kamaugh Maps
69
A
8
C
In general, one approach in digital design is to transform a truth table into a sum-of-products equation, which you then simplify as much as possible to get a practical logic circuit. D
y
5-4 KARNAUGH MAPS
Many engineers and technicians don't simplify equations with boolean algebra. Instead, they use a method based on
Karnaugh maps. This section tells you how to construct a
Kamaugh map.
(a)
8
A
8
C
A
D
A
y
8
8
8
8
8
D D []
(a)
.4
A
A
A
(b)
8
8
(c)
8
8
(b)
Fig. 5-9
(d)
(e)
Fig. 5-10 Two-variable Kamaugh map.
or as
Y
=
(A
+
D)(B
+
C)
(5-21)
In this case, the variables are first ORed, then the logical sums are ANDed. Figure 5-9b illustrates the logic circuit.
Notice it has only six input gate leads and is simpler than the circuit of Fig. 5-9a.
Final Example
In Sec. 5-2 we derived this sum-of-products equation from a truth table:
Y = ABCD
+ ABCD + ABCD
(5-22)
Figure 5-7 a shows the sum-of-products circuit. It has 15 input gate leads. We can factor the equation as
Y
= ACD(B
+B) + ABCD
or as
Y = ACD
+ ABCD
(5-23)
Figure 5-7 b shows the equivalent logic circuit; it has only nine input gate leads.
70
Digital Computer Electronics
Two-Variable Map
Suppose you have a truth table like Table 5-5. Here's how to construct the Kamaugh map. Begin by drawing Fig.
5-1 Oa. Note the order of Q!e variables and their complements; the vertic~! column has A followed by A, and the horizontal row has B followed by B.
Next, look for output 1s in Table 5-5. The first 1 output to appear is for the input of A_= 1 and B = 0. The fundamental product for this is AB. Now, enter a 1 on the
Kamaugh mae__as shown in Fig. 5-lOb. This 1 represen~ the product AB because the 1 is in the A row and the B column. Similarly, Table 5-5 has an output 1 appearing for an input of A = 1 and B = 1. The fundamental product for this is AB. When you enter a 1 on the Kamaugh map to represent AB, you get the map of Fig. 5-lOc.
The final step in the construction of the Kamaugh map is to enter Os in the remaining spaces. Figure 5-lOd shows how the Karnaugh map looks in its final form.
Here's another example of a two-variable map. In Q!e truth t~ble of Table 5-6, the fundamental products are AB and AB. When 1s are entered on the Kamaugh map for these products and Os for the remaining spaces, the completed map looks like Fig. 5-10e.
TABLE 5-5
TABLE 5-6
CD
CD
CD
CD
CD
B
y
A
B
y
AB
AB
0 0
0 .1
0
0
0
0
0
0
0
AB
AB
AB
AB
0
1
AB
AB
A
0
c
c
c
AB
AB
AB
AB
AB
AB
AB
AB
AB
AB
AB
AB
CD
CD
CD
0
0
c
0
0
AB
0
0
AB
0
0
AB
0
0
0
AB
0
0
0
0
(c)
(b)
(a)
CD
c
0
CD
CD
(b)
(a}
c
CD
0
(c)
Fig. 5-11 Three-variable Karnaugh map.
Fig. 5-12 Four-variable Karnaugh map.
Three-Variable Map
Four-Variable Map
Suppose you have a truth table like Table 5-7. Begin by drawing Fig. 5-lla. It is especially important to notice the order of the variab~~ a~d their compleEJ-ents. The vertical column is labeled A B, AB, AB, and AB. This order is not a binary progression; instead it follows the order of 00, 01,
11, and 10. The reason for this is explained in the derivation of the Karnaugh method; briefly, it's done so that only one variable changes from complemented to uncomplemented form (or vice versa).
Next, look for output 1s in Tabl~ 5J.. Th~fundamental products for these 1 outputs are ABC, ABC, and ABC.
Enter these Is on the Karnaugh map (Fig. 5-11b). The final step is to enter Os in the remaining spaces (Fig. 5-llc).
This Karnaugh map is useful because it shows the fundamental products needed for the sum-of-products circuit.
Many MSI circuits process binary words of 4 bits each
(nibbles). For this reason, logic circuits are often designed to handle four variables (or their complements). This is why the four-variable map is the most important.
Here's an example of constructing a four-variable map.
Suppose you have the truth table of Table 5-8. The first step is to draw the blank map of Fig. 5-12a. Again, notice the progression. The vertical column is labeled AB, AB,
TABLE 5-8
A
TABLE 5-7
A
0
0
0
0
B
0
0
c
0
1
0
1
0
0
0
1
0
y
B
C
D
Y
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
I
1
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
1
0
1
0
1
0
1
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
Chapter 5
[
__ _
Boolean Algebra and Karnaugh Maps
71
AB, and AB. The horizontal row is labeled CD, CD, CD, and CD.
In Table 5-8 the output 1s have these fundamental products:ABCD, ABCD, ABCD, andABCD. After entering
Is on the Kamaugh map, you will have Fig. 5-12b. The final step of filling in Os results in the completed map of
Fig. 5-12c.
goes from uncomplemented to complemented form (D to
B, and C remain uncomplemented). Whenever this happens, you can eliminate the variable that changes form.
D). The other variables don't change form (A,
Algebraic Proof
The sum-of-products equation corresponding to Fig. 5-13a
IS
5-5 PAIRS, QUADS, AND OCTETS
Y = ABCD
There is a way of using the Karnaugh map to get simplified logic circuits. But before you can understand how this is done, you will have to learn the meaning of pairs, quads, and octets.
+ ABCD
which factors into
Y = ABC(D +D)
Since D is ORed with D, the equation reduces to
CD
CD
CD
CD
0
0
0
0
AB
0
0
0
0
AB
0
0
AB
0
0
AB
CD
CD
CD
CD
Y =ABC
AB
0
0
0
0
AB
0
0
0
0
AB
0
0
AB
0
0
A pair of adjacent 1s is like those of Fig 5-l3a always means that the sum-of-products equation will have a variable and a complement that drop out.
For easy identification, it is customary t encircle a pair of adjacent Is, as shown in Fig. 5-13b. hen when you look at the map, you can tell at a glance t at one variable and its complement will drop out of the bo lean equation.
In other words, an encircled pair of ls lik those of Fig.
5-l3b no longer stands ~r the ORing o two separate products, ABCD and ABCD. The encircled pair should be visualized instead as representing a single r duced product
ABC.
Here's another example. Figure 5-13c s ows a pair of
1s that are v~ically ~ja~ent. These 1s co espond to the product ABCD and ABCD. Notice that on y one variable ch~nges from uncomplemented to comple ented form (B to B); a~other variables retain their original f rm. Therefore,
B and B drop out. This ~eans that the e circled pair of
Fig. 5-13c represents ACD.
From now on, whenever you see a pair of adjacent ls, eliminate the variable that goes from co plemented to uncomplymented form. A glance at Fig. -13d indicates
~at B changes form; therefore, the pair f 1s represents
ACD. Likewise, D_0anges form in Fig. 5- 3e; so the pair of ls stands for ABC.
If more than one pair exists on a Kam ugh map, you can OR the simplified products to get the bo lean equa~o_E_.
For instance, the lower p~ of Fig. 5-13fr presents ACD.
The upper pair stands for ABD. The corresp nding boolean equation for this map is
-
0
0
CD
CD
CD
CD
AB
0
0
0
0
AB
AB
0
0
0
0
AB
0
0
0
0
0
CD
CD
CD
0
0
0
AB
0
0
0
AB
0
0
0
0
0
0
0
0
-
-
AB
0
(d)
CD
CD
CD
CD
AB
0
0
0
0
0
AB
occ=Do
0
0
AB
0
0
0
0
0
AB
0
0
0
CD
CD
CD
CD
AB
0
0
0
0
AB
0
0
0
AB
0
0
cc=D
0
CD
(c)
AB
0
(b)
(a)
AB
cr::::::D
(e)
(f)
Fig. 5-13 Pairs on a Karnaugh map.
Y = ACD
Pairs
The map of Fig. 5-13a contains a pair of Is that are horizontally adjacent. The first 1 represents th~ product
ABCD; the second I stands for the product ABCD. As we move from the first 1 to the second 1, only one variable
72
Digital Computer Electronics
+ ABD
The Quad
A quad is a group of four 1s that are end t end, as shown in Fig. 5-14a, or in the form of a square, a shown in Fig.
co
CD
CD
CD
AB
0
0
0
0
AB
0
0
0
0
5-l4b. When you see a quad, always encircle it because it
leads to a simpler product. In fact, a quad means that two variables and their complements drop out of the boolean equation. Here's why a quad eliminates two variables. Visualize the four ls of Fig. 5-~a as two pairs (Fig. 5-14c). The first pair represents ABC; the second pair stands for ABC.
The boolean equation for these two pairs is
AB
AB
0
CD
CD
CD
CD
AB
0
0
0
0
AB
0
0
0
0
AB
AB
1
1
1
(b)
(a)
Y =ABC+ ABC
DO
Fig. 5-15 Octets on a Karnaugh map.
This factors into
Y = AB(C
+
C)
The Octet
which reduces to
An octet is a group of eight adjacent Is like those of Fig.
5-I5a. An octet always eliminates three variables and their
y = AB
complements. Here's why. Visualize the octet as two quads
(Fig. 5-15b). The equation for these two quads is
So the quad of Fig. 5-l4a represents a product where two variables and their complements drop out.
A similar proof applies to all quads. There's no need to go through the algebra again. Merely determine which variables go from complemented to uncomplemented form; these are the variables that drop out.
For instance, look at the quad of Fig. 5-14b. Pick any I as a starting point. When you move horizontally, D is the variable that changes form. When you move vertically, B changes form. Therefore, the simplified equation is
Y = AC
AB
-
AB
AB
-
AB
CD
CD
CD
CD
0
0
0
0
0
0
0
0
~
0
0
0
0
CD
CD
CD
CD
AB
0
0
0
0
AB
0
0
0
0
AB
0
0
A$
0
0
(b)
(a)
0
1
Y
=
Y
= A(C
AC
+
AC
Factoring gives
+
C)
But this reduces to
Y=A
So the octet of Fig. 5-15a means that three variables and their complements drop out of the corresponding product.
A similar proof applies to any octet. From now on, don't bother with the algebra. Just step through the 1s of the octet and determine which three variables change form.
These are the variables that drop out.
5-6 KARNAUGH SIMPLIFICATIONS
You have seen how a pair eliminates one variable, a quad eliminates two variables, and an octet eliminates three variables. Because of this, you should encircle the octets first, the quads second, and the pairs last. In this way, the greatest simplification takes place.
CD
CD
CD
CD
AB
0
0
0
0
An Example
AB
0
0
0
0
Suppose you've translated a truth table into the Kamaugh map shown in Fig. 5-l6a. Look for octets first. There are none. Next, look for quads. There are two. Finally, look for pairs. There is one. If you do it correctly, you arrive at Fig. 5-16b.
The pair represents the simplified product ABD, the lower quad stands for AC, and the quad on the right
AB
-
AB
cc:=Dcc:::D
0
0
0
(c)
Fig. 5-14 Quads on a Karnaugh map.
0
Chapter 5
Boolean Algebra and Karnaugh Maps
73
CD
AB
0
AB
0
CD
CD
CD
CD
AB
0
0
AB
0
AB
0
AB
AB
0
AB
0
CD
CD
CD
CCD~
0
0
1
0
0
represents CD. By ORing these simplified products, you get the boolean equation for the map
ABD
=
+ AC + CD
(5-26)
Y =BCD+ BCD
0
Fig. 5-16
Y
Another thing to know about is rolling. In Fig. 5-17c, the pairs result in the equation
0
(b)
(a)
Rolling the Map
(5-24)
Visualize picking up the Kamaugh map and rolling it so that the left side touches the right side. If you're visualizing correctly, you will realize the two pairs actually form a quad. To indicate this, draw half circles around each pair, as shown in Fig. 5-17d. From this viewpoint, the quad of
Fig. 5-17d has the equation
Y
=
(5-27)
BD
Why is rolling valid? Because Eq. 5-26 can be simplified to Eq. 5-27. Here's the proof. Start with Eq. 5-26:
Overlapping Groups
When you encircle groups, you are allowed to use the same
1 more than once. Figure 5-17a illustrates the idea. The simplified equation for the overlapping groups is
Y =BCD+ BCD
This factors into
Y
BD(C
=
+
C)
(5-25)
Y =A+ BCD
which reduces to
It is valid to encircle the Is as shown in Fig. 5-17b, but then the isolated 1 results in a more complicated equation:
Y =A+ ABCD
This requires a more complicated logic circuit than Eq.
5-25. So always overlap groups if possible; that is, use the
1s more than once to get the largest groups you can.
CD
AB
CD
0
0
CD
0
CD
0
CD
CD
CD
0
0
0
0
AB
AB
0
CD
0
0
AB
AB
-
AB
c
(a)
AB
AB
CD
CD
CD
CD
0
0
0
0
0
0
0
0
-
AB
0
0
a
0
CD
CD
CD
CD
AB
0
0
0
0
0
AB
0
0
0
0
AB
0
0
AB
0
CD
CD
CD
CD
AB
0
0
0
0
AB
0
AB
0
AB
0
%
1
(a)
a a 0
0
0
(b)
Fig. 5-18 Redundant group.
a
0
CD
CD
CD
CD
AB
0
0
0
0
AB
0
AB
)
0
0
0
(
AB
0
0
0
0
(c)
Fig. 5-17 Overlapping and rolling.
74
BD
(b)
-
AB
1
=
This final equation represents a rolled quad like Fig. 5-17 d.
Therefore, 1s on the edges of a Kamaugh map can be grouped with Is on opposite edges.
CD
AB
AB
Y
Digital Computer Electronics
(d)
Redundant Groups
After you finish encircling groups, there is one more thing to do before writing the simplified boolean equation: eliminate any group whose 1s are completely overlapped by other groups. (A group whose 1s are all overlapped by other groups is called a redundant group.)
Here is an example. Suppose you have encircled the three pairs shown in Fig. 5-18a. The boolean equation then is Y = BCD + ABD + ACD
At this point, you should check to see if there are any redundant groups. Notice that the 1s in the inner pair are completely overlapped by the outside pairs. Because of this, the inner pair is a redundant pair and can be eliminated to get the simpler map of Fig. 5-18b. The equation for this map is
Y =BCD
+ ACD
Since this is a simpler equation, it means a simpler logic circuit. This is why you should eliminate redundant groups if they exist.
SOLUTION
There are no octets, but there is a quad, as shown in Fig.
5-19b. By overlapping we can find two more quads (Fig.
5-19c). Finally, overlapping gives us the pair of Fig.
5-19d.
The horizontal quad of Fig. 5-19d corresponds to a simplified product of AB. The square quad on the right corresponds to AC, while the one on the left stands for AD.
The pair represents BCD. By ORing these products we get the simplified equation
Y
Summary
2.
3.
4.
5.
6.
AB
+ AC + AD + BCD
A
8
C
D
Enter a 1 on the Karnaugh map for each fundamental product that corresponds to 1 output in the truth table.
Enter Os elsewhere.
Encircle the octets, quads, and pairs. Remember to roll and overlap to get the largest groups possible.
If any isolated 1s remain, encircle them.
Eliminate redundant groups if they exist.
Write the boolean equation by ORing the products corresponding to the encircled groups.
Draw the equivalent logic circuit.
EXAMPLE
(5-28)
Figure 5-20 shows the equivalent logic circuit.
Here's a summary of how to use the Karnaugh map to simplify logic circuits:
1.
=
5-l
y
Fig. 5-20
What is the simplified boolean equation for the Karnaugh map of Fig. 5-l9a?
EXAMPLE
CD
CD
CD
CD
AB
0
0
0
0
AB
AB
0
0
0
AB
AB
AB
CD
CD
CD
0
0
0
0
0
0
-
AB
0
CD
AB
0
~
0
1
1
5-2
As you know from Chap. 4, the NAND gate is the least expensive gate in the 7400 series. Because of this, ANDOR circuits are usually built as equivalent NAND-NAND circuits. Convert the AND-OR circuit of Fig. 5-20 to a NAND-NAND circuit using 7400-series devices.
1
SOLUTION
(b)
(a)
AB
AB
AB
AB
CD
CD
CD
CD
0
0
0
0
0
0
0
:=m
1
(c)
Fig. 5-19
AB
-
AB
AB
AB
CD
CD
CD
CD
0
0
0
0
0
0
(0
0
~1
~
Th
1
1
0
(d)
-j
Replace each AND gate of Fig. 5-20 by a NAND gate and replace the final OR gate by a NAND gate. Figure 5-21 is the De Morgan equivalent of Fig. 5-20. As shown, we can build the circuit with a 7400, a 7410, and a 7420.
5-7 DON'T-CARE CONDITIONS
Sometimes, it doesn't matter what the output is for a given input word. To indicate this, we use an X in the truth table instead of a 0 or a 1. For instance, look at Table 5-9. The
Chapter 5
Boolean Algebra and Kamaugh Maps
75
A
8
C
D
CD
~--------,
I
I
74oo
._,_-r-+---r-1,
3
I
A8
CD
CD
CD
CD
CD
A8
0
0
CD
CD
0
k>-'~f----,
~
A8
y
L _______ J
2
A8
0
A8
X
A8
X
X
X
X
A8
X
X
X
X
X
(b)
(a)
I
7420
A
12
.-~----~
0
.4
8
8 c
c
D
D
b-----~
13
7410
Fig. 5-21
NAND-NAND
circuit using TTL gates. y output is an X for any input word from 1000 through 1111.
The X's are called don't cares because they can be treated either as Os or 1s, whichever leads to a simpler circuit.
Figure 5-22a shows the Kamaugh map for Table 5-9.
X's are used for ABCD, ABCD, AiiciS, ABCD, ABCD,
ABCD, ABCD, and ABCD because these are don't cares in the truth table. Figure 5-22b shows the most efficient way to encircle the groups. Notice two crucial ideas. First, we visualize all X's as Is and try to form the largest groups that include the real 1s. This gives us three quads. Second, we visualize all remaining X's as Os. In this way, the X's are used to the best advantage. We are free to do this because the don't cares can be either Os or 1s, whichever we prefer.
A
B
c
D
y
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
1
0
0
0
0
0
1
0
1
0
1
0
1
0
0
0
1
0
1
X
X
X
X
X
X
X
X
76
Figure 5-22b implies the simplified boolean equation
Y
Digital Computer Electronics
=
BD +CD+ CD
Figure 5-22c is the simplified logic circuit. This network has nine input gate leads.
EXAMPLE
TABLE 5-9
0
0
(c)
Fig. 5-22 Don't cares.
AND-OR
5-3
Recall that BCD numbers express each decimal digit as a nibble: 0 to 9 are encoded as 0000 to 1001. Especially important, nibbles 1010 to 1111 are never used in a BCD system. Table 5-10 shows a truth table for use in a BCD system.
As you see, don't cares appear for 1010 through 1111.
Construct the Kamaugh map and show the simplified logic circuit. SOLUTION
Figure 5-23a illustrates the Kamaugh map. The largest group we can form is the pair shown in Fig. 5-23b. The boolean equation is
Y =BCD
Figure 5-23c is the simplified logic circuit.
TABLE 5-10
A
B
c
D
y
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
X
X
X
X
X
X
0
0
0
0
t
0
0
0
0
0
1
0
0
\~
0
1
0
1
0
1
0
0
1'
0
CD
CD
CD
CD
AB
0
0
0
0
0
AB
0
0
X
X
AB
X
X
X
X
AB
0
0
CD
CD
CD
CD
AB
0
0
0
0
AB
0
0
AB
X
X
AB
0
0
X
X
X
(b)
(a)
'/
A .4
Q
0
8
8 c
c
D jj y (c)
Fig. 5-23 Don't cares in a BCD system.
)
GLOSSARY bus A group of wires carrying digital signals. don't care An output that may be either low or high without affecting the operation of the system. fundamental product The logical product of variables and complements that produces a high output for a given input condition. Karnaugh map A graphical display of the fundamental products in a truth table. octet A group of eight adjacent Is on a Kamaugh map.
pair A group of two adjacent Is on a Karnaugh map.
These 1s may be horizontally or vertically aligned. quad A group of four adjacent 1s on a Karnaugh map. redundant group A group of Is on a Karnaugh map all of which are overlapped by other groups. sum-of-products circuit An AND-OR circuit obtained by
ORing the fundamental products that produce output Is in a truth table.
SELF-TESTING REVIEW
Read each of the following and provide the missing words.
Answers appear at the beginning of the next question.
5.
1.
2.
3.
4.
Digital design often starts by constructing a _ __ table. By ORing the products, you get a sum-of-products equation.
(truth, fundamental) A preliminary guide for comparing the simplicity of logic circuits is to count the number of input leads. (gate) A bus is a group of carrying digital signals. In the typical microcomputer, the microprocessor, memory, and 1/0 units communicate via buses.
(wires) One way to simplify the sum-of-products
6.
7.
equation is to use boolean algebra. Another way is the map.
(Karnaugh) A pair eliminates one variable, a
_ _ _ _ eliminates two variables, and an octet eliminates variables. Because of this, you should encircle the first, the quads next, and the pairs last.
(quad, three, octets) NAND-NAND circuits are equivalent to AND-OR circuits. This is important because
_ _ _ _ gates are the least expensive gates in the
7400 series.
(NAND) When a truth table has don't cares, we enter
X's on the Kamaugh map. These can be treated as Os or Is, whichever leads to a simpler logic circuit.
Chapter 5
Boolean Algebra and Kamaugh Maps
77
PROBLEMS
5-1.
5-2.
5-3.
What are the fundamental products for each of the inputs words ABCD = 0010, ABCD = 1101,
ABCD = 1110?
A truth table has output 1s for each of these inputs: a. ABCD = 0011
b. ABCD = 0101
c. ABCD = 1000
d. ABCD = 1101
What are the fundamental products?
Draw the logic circuit for this boolean equation:
Y = ABCD + ABCD + ABCD + ABCD
5-4.
5-5.
Output 1s appear in the truth table for these input conditions: ABCD = 0001, ABCD = 0110, and
ABCD = 1110. What is the sum-of-products equation? Draw the AND-OR circuit for
5-8.
5-9.
5-10.
5-11.
5-12.
5-13.
5-14.
5-15.
5-16.
5-17.
5-18.
5-19.
5-20.
5.21.
Y = ABCD + ABCD + ABCD
5-6.
5-7.
How many input gate leads does this circuit have?
A truth table has output Is for these inputs:
ABCD = 0011, ABCD = 0110, ABCD =
1001, and ABCD = 1110. Draw the Kamaugh map showing the fundamental products.
A truth table has four input variables. The first eight outputs are Os, and the last eight outputs are
Is. Draw the Kamaugh map.
TABLE 5-11
B
c
D
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
I
1
0
0
0
0
0
I
I
0
0
0
1
0
y3 y2 yi Yo
I
0
0
1
0
I
l
0
0
0
1
0
0
0
I
0
0
0
I
0
0
0
I
0
0
0
0
0
I
1
0
0
0
1
1
0
0
I
Digital Computer Electronics
0
0
1
0
I
I
0
0
0
0
0
I
0
0
78
5.23
TABLE 5-12
A
1
0
5.22
Draw the Kamaugh map for the Y3 output of
Table 5-11. Simplify as much as possible; then draw the logic circuit.
Use the Karnaugh map to work out the simplified logic circuit for the Y2 output of Table 5-11.
Repeat Prob. 5-9 for the Y1 output.
Repeat Prob. 5-9 for the Y0 output.
Use the Karnaugh map to work out the simplified logic circuit for the Y 3 output of Table 5-12.
Repeat Prob. 5-12 for the Y2 output.
Repeat Prob. 5-12 for the Y1 output.
Repeat Prob. 5-12 for Y0 output.
A+ 0 =?
A· 1 = ?
A + 1 = ?
A· 0 =?
Use the duality theorem to derive another boolean relation from:
A+ AB =A+ B
Use the commutative law to complete the following equations.
a. A+ B =
b. AB =
Use the associative law to complete the following equations. a. A+ (B + C) =
b. A(BC) =
Use the distributive law to complete the equation
A(B + C) =
1
0
0
A
B
c
D
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 lJ 0
1
0
0
0
0
0
1
0
I
I
0
0
0
0
1
0
0
0
0
y3 y2 yi Yo
0
0
0
1
0
1
0
0
X
X
X
X
X
X
1
0
0
0
1
1
0
0
X
X
X
X
X
X
0
0
1
0
I
0
1
0
0
X
X
X
X
X
X
0
0
I
0
X
X
X
X
X
X
Computer
Electronics
Third Edition
Albert Paul Malvino, Ph.D.
Jerald A. Brown
~
1
I
I-
I
I
I
I
I
_j
1
I
I
I
GLENCOE
McGraw-Hill
New York, New York
Columbus, Ohio
Woodland Hills, California
Peoria, Illinois
This textbook was prepared with the assistance of Publishing Advisory Service.
LSI circuit photo: Manfred Kage/Peter Arnold Inc.
To my wife, Joanna, who encourages me to write.
And to my daughters, Joanna, Antonia, Lucinda,
Patricia, and Miriam, who keep me young.
-A.P.M .
. . to my wife Vickie dearest friend fellow adventurer love of my life
-J.A.B.
Library of Congress Cataloging-in-Publication Data
Malvino, Albert Paul.
Digital computerelectronics I Albert Paul Malvino, Jerald A.
Brown. - 3rd ed.
p.
em.
Includes index.
ISBN 0-02-800594-5 (hardcover)
1. Electronic digital computers. 2. Microcomputers. 3. Intel
8085 (Microprocessor) I. Brown, Jerald A. II. Title.
TK7888.3.M337 1993
621.39' 16-dc20
92-5895
CIP
Digital Computer Electronics, Third Edition
Imprint 1999
Copyright© 1993, 1983 by Glencoe/McGraw-Hill. All rights reserved. Copyright© 1983, 1977 by
McGraw-Hill, Inc. All rights reserved. Printed in the United States of America. Except as permitted under the United States Copyright Act, no part of this publication may be reproduced or distributed in any form or by any means, or stored in a database or retrieval system, without prior written permission of the publisher.
ISBN 0-02-800594-5
Printed in the United States of America.
456789101112
004/043
0302010099
Contents
PREFACE
vi
CHAPTER 6. ARITHMETIC-LOGIC UNITS
79
6-1. Binary Addition 6-2. Binary Subtraction
6-3. Half Adders 6-4. Full Adders 6-5. Binary
Adders 6-6. Signed Binary Numbers 6-7. 2's
Complement 6-8. 2's-Complement Adder-Subtracter
PART 1
Digital Principles 1
CHAPTER I. NUMBER SYSTEMS AND
CODES I
1-1. Decimal Odometer
1-2. Binary Odometer
1-3. Number Codes
1-4. Why Binary Numbers Are
Used
1-5. Binary-to-Decimal Conversion
1-6. Microprocessors
1-7. Decimal-to-Binary
Conversion
1-8. Hexadecimal Numbers
1-9. Hexadecimal-Binary Conversions
1-10. Hexadecimal-to-Decimal Conversion
1-11. Decimal-to-Hexadecimal Conversion
1-12. BCD Numbers
1-13. The ASCII Code
CHAPTER 2. GATES
CHAPTER 7. FLIP-FLOPS
90
7-1. RS Latches 7-2. Level Clocking 7-3. D Latches
7-4. Edge-Triggered D Flip-Flops 7-5. Edge-Triggered
JK Flip-Flops
7-6. JK Master-Slave Flip-Flop
CHAPTER 8. REGISTERS AND
COUNTERS I06
8-1.
8-3.
8-5.
8-7.
8-9.
Buffer Registers 8-2. Shift Registers
Controlled Shift Registers 8-4. Ripple Counters
Synchronous Counters 8-6. Ring Counters
Other Counters
8-8. Three-State Registers
Bus-Organized Computers
I9
2-1. Inverters 2-2. OR Gates
2-4. Boolean Algebra
2-3.
AND
Gates
I30
9-1. ROMs
9-2. PROMs and EPROMs 9-3. RAMs
9-4. A Small TTL Memory 9-5. Hexadecimal
Addresses
CHAPTER 3. MORE LOGIC GATES
32
3-1. NOR Gates 3-2. De Morgan's First Theorem
3-3. NAND Gates 3-4. De Morgan's Second Theorem
3-5. EXCLUSIVE-OR Gates 3-6. The Controlled
Inverter 3-7. EXCLUSIVE-NOR Gates
CHAPTER 4. TTL CIRCUITS
CHAPTER 9. MEMORIES
48
PART 2
SAP (Simple-as-Possible)
Computers 140
CHAPTER IO. SAP-I
I40
4-1. Digital Integrated Circuits 4-2. 7400 Devices
4-3. TTL Characteristics 4-4. TTL Overview
4-5. AND-OR-INVERT Gates 4-6. Open-Collector Gates
4-7. Multiplexers
I 0-1 . Architecture
I 0-2. Instruction Set
10-3. Programming SAP-I
10-4. Fetch Cycle
10-5. Execution Cycle
10-6. The SAP-I
Microprogram
I 0-7. The SAP-I Schematic Diagram
10-8. Microprogramming
CHAPTER 5. BOOLEAN ALGEBRA AND
KARNAUGH MAPS 64
CHAPTER II. SAP-2
5-1. Boolean Relations 5-2. Sum-of-Products Method
5-3. Algebraic Simplification 5-4. Karnaugh Maps
5-5. Pairs, Quads, and Octets 5-6. Karnaugh
Simplifications 5-7. Don't-Care Conditions
I73
Il-l. Bidirectional Registers
11-2. Architecture
11-3. Memory-Reference Instructions
11-4. Register
Instructions
11-5. Jump and Call Instructions
11-6. Logic Instructions
11-7. Other Instructions
11-8. SAP-2 Summary
iii
------
CHAPTER 12. SAP-3
CHAPTER 18. ARITHMETIC AND FLAGS
195
12-1. Programming Model
12-2. MOV and MVI
12-3. Arithmetic Instructions
12-4. Increments,
Decrements, and Rotates
12-5. Logic Instructions
12-6. Arithmetic and Logic Immediates
12-7. Jump
Instructions
I2-8. Extended-Register Instructions
12-10. Stack Instructions
12-9. Indirect Instructions
Computer Hardware
Definition of a Microprocessor
Some Common Uses for Microprocessors
Microprocessors Featured in This Text
Access to Microprocessors
CHAPTER 20. SHIFT AND ROT ATE
INSTRUCTIONS 319
CHAPTER 14. PROGRAMMING AND
LANGUAGES 216
Relationship between Electronics and Programming
Programming
14-3. Fundamental Premise
Flowcharts
14-5. Programming Languages
Assembly Language
14-7. Worksheets
CHAPTER 15. SYSTEM OVERVIEW
224
New Concepts
15-1. Computer Architecture
15-2. Microprocessor Architecture
Specific Microprocessor Families
15-4. 6800/6808 Family
15-3. 6502 Family
15-6. 8086/8088 Family
15-5. 8080/8085/Z80 Family
CHAPTER 16. DATA TRANSFER
INSTRUCTIONS 240
New Concepts
16-1. CPU Control Instructions
16-2. Data Transfer Instructions
Specific Microprocessor Families
16-4. 6800/6808 Family
16-3. 6502 Family
16-6. 8086/8088 Family
16-5. 8080/8085/Z80 Family
CHAPTER 17. ADDRESSING MODES-I
263
New Concepts
17-1. What Is an Addressing Mode'?
17-2. The Paging Concept
17-3. Basic Addressing Modes
17-4. 6502 Family
Specific Microprocessor Families
17-6. 8080/8085/Z80 Family
17-5. 6800/6808 Family
17-7. 8086/8088 Family
iv
Contents
New Concepts
18-1. Microprocessors and Numbers
18-2. Arithmetic Instructions
18-3. Flag Instructions
Specific Microprocessor Families
18.4 6502 Family
18-5. 6800/6808 Family
18-6. 8080/8085/Z80 Family
18-7. 8086/8088 Family
New Concepts
19-1 . The AND Instruction
19-2. The OR Instruction
19-3. The EXCLUSIVE-OR (EOR, XOR) Instruction
19-4. The NOT Instruction
19-5. The NEG (NEGate) Instruction
Specific Microprocessor Families
19-6. 6502 Family
19-8. 8080/8085/Z80 Family
19-7. 6800/6808 Family
19-9. 8086/8088 Family
CHAPTER 13. INTRODUCTION TO
MICROPROCESSORS 213
14-1.
14-2.
14-4.
14-6.
270
CHAPTER 19. LOGICAL INSTRUCTIONS
305
PART 3
Programming Popular
Microprocessors 213
13-1 .
13-2.
13-3.
13-4.
13-5.
-··----
New Concepts 20-1. Rotating 20-2. Shifting
20-3. An Example Specific Microprocessor Families
20-4. 6502 Family 20-5. 6800/6808 Family
20-6. 8080/8085/Z80 Family 20-7. 8086/8088 Family
CHAPTER 21. ADDRESSING MODES-II 329
New Concepts 21-1. Advanced Addressing Modes
Specific Microprocessor Families 21-2. 6502 Family
21-3. 6800/6808 Family 21-4. 8080/8085/Z80 Family
21-5. 8086/8088 Family
CHAPTER 22. BRANCHING AND LOOPS 342
New Concepts 22-1. Unconditional Jumps
22-2. Conditional Branching
22-3. Compare and Test Instructions
22-4. Increment and Decrement Instructions
22-5. Nested Loops
Specific Microprocessor Families 22-6. 6502 Family
22-7. 6800/6808 Family 22-8. 8080/8085/Z80 Family
22-9. 8086/8088 Family
CHAPTER 23. SUBROUTINE AND STACK
INSTRUCTIONS 363
New Concepts 23-1. Stack and Stack Pointer
23-2. Branching versus Subroutines
23-3. How Do Subroutines Return?
23-4. Pushing and Popping Registers
Specific Microprocessor Families 23-5. 6502 Family
23-6. 6800/6808 Family 23-7. 8080/8085/Z80 Family
24-8. 8086/8088 Family
PART 4
Microprocessor Instruction
Set Tables 379
A.
Expanded Table of 8085/8080 and Z80 (8080 Subset)
Instructions Listed by Category
381
Mini Table of 8085/8080 and Z80 (8080 Subset)
Instructions Listed by Category
410
Condensed Table of 8085/8080 and Z80 (8080)
Instructions Listed by Category
415
Condensed Table of 8085/8080 and Z80 (8080 Subset)
Instructions Listed by Op Code
417
Condensed Table of 8085/8080 and Z80 (8080 Subset)
Instructions Listed Alphabetically by 8085/8080
Mnemonic
419
Condensed Table of 8085/8080 and Z80 (8080 Subset)
Instructions Listed Alphabetically by Z80 Mnemonic
421
B.
Expanded Table of 6800 Instructions Listed by Category
422
Short Table of 6800 Instructions Listed Alphabetically
434
Short Table of 6800 Instructions Listed by Category
437
c.
Expanded Table of 8086/8088 Instructions Listed by
Category
445
Condensed Table of 8086/8088 Instructions Listed by
Category
465
Condensed Table of 8086/8088 Instructions Listed
Alphabetically
469
D.
Expanded Table of 6502 Instructions Listed by Category
471
Short Table of 6502 Instructions Listed by Category
478
Condensed Table of 6502 Instructions Listed by Category
480
Condensed Table of 6502 Instructions Listed
Alphabetically
481
Condensed Table of 6502 Instructions Listed by Op Code
482
APPENDIXES
485
1. The Analog Interface 2. Binary-HexadecimalDecimal Equivalents 3. 7400 Series TTL
4. Pinouts and Function Tables 5. SAP-I Parts List
6. 8085 Instructions 7. Memory Locations: Powers of 2
8. Memory Locations: 16K and 8K Intervals
9. Memory Locations: 4K Intervals
10. Memory
Locations: 2K Intervals 11. Memory Locations: IK
Intervals
12. Programming Models
Condensed Table of 6800 Instructions Listed by Category
441
Condensed Table of 6800 Instructions Listed
Alphabetically
443
Condensed Table of 6800 Instructions Listed by Op Code
444
ANSWERS TO ODD-NUMBERED PROBLEMS
513
INDEX
519
Contents
V
Preface
Textbooks on microprocessors are sometimes hard to understand. This text attempts to present the various aspects of microprocessors in ways that are understandable and interesting. The only prerequisite to using this textbook is an understanding of diodes and transistors.
A unique aspect of this text is its wide range. Whether you are interested in the student-constructed SAP (simpleas-possible) microprocessor, the 6502, the 6800/6808, the
8080/8085/Z80, or the 8086/8088, this textbook can meet your needs.
The text is divided into four parts. These parts can be used in different ways to meet the needs of a wide variety of students, classrooms, and instructors.
Part I, Digital Principles, is composed of Chapters 1 to
9. Featured topics include number systems, gates, boolean algebra, flip-flops, registers, counters, and memory. This information prepares the student for the microprocessor sections which follow.
Part 2, which consists of Chapters 10 to 12, presents the
SAP (simple-as-possible) microprocessor. The student constructs this processor using digital components. The SAP processor contains the most common microprocessor functions. It features an instruction set which is a subset of that of the Intel 8085-leading naturally to a study of that microprocessor. Part 3, Programming Popular Microprocessors (Chapters
13 to 23), simultaneously treats the MOS/Rockwell 6502, the Motorola 6800/6808, the Intel 8080/8085 and Zilog
Z80, and the 16-bit Intel 8086/8088. Each chapter is divided into two sections. The first section presents new concepts; second section applies the new concepts to each microprocessor family. Discussion, programming examples, and problems are provided. The potential for comparative study is excellent.
This part of the text takes a strong programming approach to the study of microprocessors. Study is centered around the microprocessor's instruction set and programming model.
The 8-bit examples and homework problems can be performed by using either hand assembly or cross-assemblers.
The 16-bit 8086/8088 examples and problems can be performed by using either an assembler or the DOS DEBUG utility. Part 4 is devoted to the presentation of the instruction sets of each microprocessor family in table form. Several tables are provided for each microprocessor family, permitting instructions to be looked up alphabetically, by op code, or by functional category, with varying levels of detail. The same functional categories are correspondingly used in the chapters in Part 3. This coordination between parts makes the learning process easier and more enjoyable.
Additional reference tables are provided in the appendixes. Answers to odd-numbered problems for Chapters 1 to 16 follow the appendixes.
A correlated laboratory manual, Experiments for Digital
Computer Electronics by Michael A. Miller, is available for use with this textbook. It contains experiments for every part of the text. It also includes programming problems for each of the featured microprocessors.
A teacher's manual is available which contains answers to all of the problems and programs for every microprocessor. In addition, a diskette (MS-DOS 360K 5V4-inch diskette) containing cross-assemblers is included in the teacher's manual.
Special thanks to Brian Mackin for being such a patient and supportive editor. To Olive Collen for her editorial work. To Michael Miller for his work on the lab manual.
And to Thomas Anderson of Speech Technologies Inc. for the use of his cross-assemblers. Thanks also to reviewers
Lawrence Fryda, Illinois State University; Malachi McGinnis, ITT Technical Institute, Garland Texas; and Benjamin Suntag.
A man of true science uses but few hard words, and those only when none other will answer his purpose; whereas the smatterer in science thinks that by mouthing hard words he understands hard things.
Herman Melville
vi
Albert Paul Malvino
Jerald A. Brown
PART 1
DIGITAL PRINCIPLES
NUMBER SYSTEMS
AND CODES
Modem computers don't work with decimal numbers.
Instead, they process binary numbers, groups of Os and 1s.
Why binary numbers? Because electronic devices are most reliable when designed for two-state (binary) operation.
This chapter discusses binary numbers and other concepts needed to understand computer operation.
1-1 DECIMAL ODOMETER
The other wheels also reset and carry. After 999 miles the odometer shows
00999
What does the next mile do? The units wheel resets and carries, the tens wheel resets and carries, the hundreds wheel resets and carries, and the thousands wheel advances by 1, to get
01000
Rene Descartes (1596-1650) said that the way to learn a new subject is to go from the known to the unknown, from the simple to the complex. Let's try it.
The Known
Everyone has seen an odometer (miles indicator) in action.
When a car is new, its odometer starts with
00000
After 1 mile the reading becomes
00001
Digits and Strings
The numbers on each odometer wheel are called digits.
The decimal number system uses ten digits, 0 through 9.
In a decimal odometer, each time the units wheel runs out of digits, it resets to 0 and sends a carry to the tens wheel.
When the tens wheel runs out of digits, it resets to 0 and sends a carry to the hundreds wheel. And so on with the remaining wheels.
One more point. A string is a group of characters (either letters or digits) written one after another. For instance,
734 is a string of 7, 3, and 4. Similarly, 2C8A is a string of 2, C, 8, and A.
Successive miles produce 00002, 00003, and so on, up to
00009
A familiar thing happens at the end of the tenth mile.
When the units wheel turns from 9 back to 0, a tab on this wheel forces the tens wheel to advance by I. This is why the numbers change to
00010
1-2 BINARY ODOMETER
Binary means two. The binary number system uses only two digits, 0 and 1. All other digits (2 through 9) are thrown away. In other words, binary numbers are strings of Os and 1s.
Reset-and-Carry
An Unusual Odometer
The units wheel has reset to 0 and sent a carry to the tens wheel. Let's call this familiar action reset-and-carry.
Visualize an odometer whose wheels have only two digits,
0 and 1. When each wheel turns, it displays 0, then I, then
1
---------
back to 0, and the cycle repeats. Because each wheel has only two digits, we call this device a binary odometer.
In a car a binary odometer starts with
0000
(zero)
After I mile, it indicates
0001
(one)
The next mile forces the units wheel to reset and carry; so the numbers change to
0010
(two)
The third mile results in
0011
(three)
What happens after 4 miles? The units wheel resets and carries, the second wheel resets and carries, and the third wheel advances by 1. This gives
0100
(four)
for 3, and so forth. Binary numbers are long when large
amounts are involved. For instance, 101010 represents decimal 42. As another example, 111I 00001111 stands for decimal 3,855.
Computer circuits are like binary odometers; they count and work with binary numbers. Therefore, you have to learn to count with binary numbers, to convert them to decimal numbers, and to do binary arithmetic. Then you will be ready to understand how computers operate.
A final point. When a decimal odometer shows 0036, we can drop the leading Os and read the number as 36.
Similarly, when a binary odometer indicates 0011, we can drop the leading Os and read the number as 11. With the leading Os omitted, the binary numbers are 0, 1, 10, 11,
100, 101, and so on. To avoid confusion with decimal numbers, read the binary numbers like this: zero, one, onezero, one-one, one-zero-zero, one-zero-one, etc.
1-3 NUMBER CODES
People used to count with pebbles. The numbers I, 2, 3 looked like e, ee, eee. Larger numbers were worse: seven appeared as eeeeeee.
Successive miles produce
Codes
0101
0110
0111
(five)
(six)
(seven)
After 8 miles, the units wheel resets and carries, the second wheel resets and carries, the third wheel resets and carries, and the fourth wheel advances by 1. The result is
1000
(eight)
1001
(nine)
The ninth mile gives
From the earliest times, people have been creating codes that allow us to think, calculate, and communicate. The decimal numbers are an example of a code (see Table
1-1). It's an old idea now, but at the time it was as revolutionary; I stands for e, 2 for ee, 3 for eee, and so forth.
Table 1-I also shows the binary code. 1 stands fore, 10 for ee, 11 for eee, and so on. A binary number and a decimal number are equivalent if each represents the same amount of pebbles. Binary 10 and decimal 2 are equivalent because each represents ee. Binary I01 and decimalS are equivalent because each stands for eeeee.
and the tenth mile produces
TABLE 1-1. NUMBER CODES
1010
(ten)
Decimal
(Try working out a few more readings on your own.)
You should have the idea by now. Each mile advances the units wheel by 1. Whenever the units wheel runs out of digits, it resets and carries. Whenever the second wheel runs out of digits, it resets and carries. And so for the other wheels. Binary Numbers
A binary odometer displays binary numbers, strings of Os and Is. The number 000 I stands for I , 00 I 0 for 2, 00 II
2
Digital Computer Electronics
0
1
2
3
4
5
6
7
8
9
Pebbles
Binary
None
•
••
•••
••••
•
••••
••••••
•••••••
••••••••
•••••••••
0
I
10
II
100
101
110
111
1000
1001
Equivalence is the common ground between us and computers; it tells us when we're talking about the same thing. If a computer comes up with a binary answer of I 0 I, equivalence means that the decimal answer is 5. As a start to understanding computers, memorize the binary-decimal equivalences of Table 1-1.
EXAMPLE
TABLE 1-2. BINARY-TO-DECIMAL
EQUIVALENCES
1-1
Figure l-1a shows four light-emitting diodes (LEDs). A dark circle means that the LED is off; a light circle means it's on. To read the display, use this code:
Decimal
Binary
Decimal
Binary
0
1
2
3
4
5
6
7
0000
0001
0010
0011
0100
0101
0110
0111
8
9
10
11
12
13
14
15
1000
1001
1010 lOll 1100
1101
1110
1111
eo eo
(b)
(a)
Therefore, you should memorize the equivalences of Table
1-2.
Fig. 1-1 LED display of binary numbers.
LED
Binary
Off
0
1-4 WHY BINARY NUMBERS
ARE USED
On
The word "computer" is misleading because it suggests a machine that can solve only numerical problems. But a computer is more than an automatic adding machine. It can play games, translate languages, draw pictures, and so on.
To suggest this broad range of application, a computer is often referred to as a data processor.
What binary number does Fig. 1-1a indicate? Fig. 1-1b?
SOLUTION
Program and Data
Figure 1-1a shows off-off-on-on. This stands for binary
0011 , equivalent to decimal 3.
Figure 1-lb is off-on-off-on, decoded as binary 0101 and equivalent to decimal 5.
EXAMPLE
Data means names, numbers, facts, anything needed to work out a problem. Data goes into a computer, where it is processed or manipulated to get new information. Before it goes into a computer, however, the data must be coded in binary form. The reason was given earlier: a computer's circuits can respond only to binary numbers.
Besides the data, someone has to work out a program, a list of instructions telling the computer what to do. These instructions spell out each and every step in the data processing. Like the data, the program must be coded in binary form before it goes into the computer.
So the two things we must input to a computer are the program and the data. These are stored inside the computer before the processing begins. Once the computer run starts, each instruction is executed and the data is processed.
1-2
A binary odometer has four wheels. What are the successive binary numbers?
SOLUTION
As previously discussed, the first eight binary numbers are
0000, 0001, 0010, 0011, 0100, 0101, 0110, and 0111. On the next count, the three wheels on the right reset and carry; the fourth wheel advances by one. So the next eight numbers are 1000, 1001, 1010, lOll, 1100, 1101, 1110, and 1111.
The final reading of 1111 is equivalent to decimal 15. The next mile resets all wheels to 0, and the cycle repeats.
Being able to count in binary from 0000 to 1111 is essential for understanding the operation of computers.
Hardware and Software
The electronic, magnetic, and mechanical devices of a computer are known as hardware. Programs are called software. Without software, a computer is a pile of ''dumb'' metal. Chapter 1
--------------
~·~
·-----
Number Systems and Codes
3
------~---
Another Code
An analogy may help. A phonograph is like hardware and records are like software. The phonograph is useless without records. Furthermore, the music you get depends on the record you play. A similar idea applies to computers.
A computer is the hardware and programs are the software.
The computer is useless without programs. The program stored in the computer determines what the computer will do; change the program and the computer processes the data in a different way.
Two-state operation is universal in digital electronics. By deliberate design, all input and output voltages are either low or high. Here's how binary numbers come in: low voltage represents binary 0, and high voltage stands for binary 1. In other words, we use this code:
Voltage
Binary
0
Low
High
Transistors
Computers use integrated circuits (ICs) with thousands of transistors, either bipolar or MOS. The parameters (~do fc 0 , gm, etc.) can vary more than 50 percent with temperature change and from one transistor to the next. Yet these computer ICs work remarkably well despite the transistor variations. How is it possible?
The answer is two-state design, using only two points on the load line of each transistor. For instance, the common two-state design is the cutoff-saturation approach; each transistor is forced to operate at either cutoff or saturation.
When a transistor is cut off or saturated, parameter variations have almost no effect. Because of this, it's possible to design reliable two-state circuits that are almost independent of temperature change and transistor variations.
For instance, the base voltages of Fig. 1-2 are low-lowhigh-high, or binary 0011. The collector voltages are highhigh-low-low, or binary 1100. By changing the base voltages we can store any binary number from 0000 to 1111 (decimal
0 to 15).
Bit
Bit is an abbreviation for binary digit. A binary number like 1100 has 4 bits; 110011 has 6 bits; and 11001100 has
8 bits. Figure 1-2 is a 4-bit register. To store larger binary numbers, it needs more transistors. Add two transistors and you get a 6-bit register. With four more transistors, you'd have an 8-bit register.
Transistor Register
Nonsaturated Circuits
Here's an example of two-state design. Figure 1-2 shows a transistor register. (A register is a string of devices that store data.) The transistors on the left are cut off because the input base voltages are 0 V. The dark shading symbolizes the cutoff condition. The two transistors on the right have base drives of 5 V.
The transistors operate at either saturation or cutoff. A base voltage of 0 V forces each transistor to cut off, while a base voltage of 5 V drives it into saturation. Because of this two-state action, each transistor stays in a given state until the base voltage switches it to the opposite state.
Don't get the idea that all two-state circuits switch between cutoff and saturation. When a bipolar transistor is heavily saturated, extra carriers are stored in the base region. If the base voltage suddenly switches from high to low, the transistor cannot come out of saturation until these extra carriers have a chance to leave the base region. The time it takes for these carriers to leave is called the saturation delay time td. Typically, td is in nanoseconds.
In most applications the saturation delay time is too short to matter. But some applications require the fastest possible
,-------------~~-------------.--------------~--o+5V
1 kD.
+5
v
ov
ov
(Approx.)
(Approx.)
10 k!l
ov
Fig. 1-2 Transistor register.
4
Digital Computer Electronics
ov
+5 v
+5 v
switching time. To get this maximum speed, designers have come up with circuits that switch from cutoff (or near cutoff) to a higher point on the load line (but short of saturation). These nonsaturated circuits rely on clamping diodes or heavy negative feedback to overcome transistor variations. Remember this: whether saturated or nonsaturated circuits are used, the transistors switch between distinct points on the load line. This means that all input and output voltages are easily recognized as low or high, binary 0 or binary l.
/
(a)
{b)
Fig. 1-3 Core register.
Magnetic Cores
Early digital computers used magnetic cores to store data.
Figure 1-3a shows a 4-bit core register. With the righthand rule, you can see that conventional current into a wire produces a clockwise flux; reversing the current gives a counterclockwise flux. (The same result is obtained if electron-flow is assumed and the left-hand rule is used.)
The cores have rectangular hysteresis loops; this means that flux remains in a core even though the magnetizing current is removed (see Fig. l-3b). This is why a core register can store binary data indefinitely. For instance, let's use the following code:
Flux
Binary
Counterclockwise
Clockwise
0
Then, the core register of Fig. 1-3b stores binary 1001, equivalent to decimal 9. By changing the magnetizing currents in Fig. 1-3a we can change the stored data.
To store larger binary numbers, add more cores. Two cores added to Fig. 1-3a result in a 6-bit register; four more cores give an 8-bit register.
The memory is one of the main parts of a computer.
Some memories contain thousands of core registers. These registers store the program and data needed to run the computer. Other Two-State Examples
The simplest example of a two-state device is the on-off switch. When this switch is closed, it represents binary 1; when it's open, it stands for binary 0.
Punched cards are another example of the two-state concept. A hole in a card stands for binary 1 , the absence of a hole for binary 0. Using a prearranged code, a cardpunch machine with a keyboard can produce a stack of cards containing the program and data needed to run a computer. Magnetic tape can also store binary numbers. Tape recorders magnetize some points on the tape (binary 1), while leaving other points unmagnetized (binary 0). By a prearranged code, a row of points represents either a coded instruction or data. In this way, a reel of tape can store thousands of binary instructions and data for later use in a computer. Even the lights on the control panel of a large computer are binary; a light that's on stands for binary 1, and one that's off stands for binary 0. In a 16-bit computer, for instance, a row of 16 lights allows the operator to see the binary contents in different computer registers. The operator can then monitor the overall operation and, when necessary, troubleshoot. In summary, switches, transistors, cores, cards, tape, lights, and almost all other devices used with computers are based on two-state operation. This is why we are forced to use binary numbers when analyzing computer action.
EXAMPLE
1-3
Figure 1-4 shows a strip of magnetic tape. The black circles are magnetized points and the white circles unmagnetized points. What binary number does each horizontal row represent? ooooe••• eooooeeo •o••o••• ooeeoooe •••ooeeo oeooeooe eeooeeoe
Fig. 1-4 Binary numbers on magnetic tape.
SOLUTION
The tape stores these binary numbers:
Row
Row
Row
Row
1
2
3
4
00001111
10000110
10110111
00110001
Chapter 1
Row 5
Row 6
Row 7
11100110
01001001
11001101
Number Systems and Codes
5
------------------~·----
(Note: these binary numbers may represent either coded instructions or data.)
A string of 8 bits is called a byte. In this example, the magnetic tape stores 7 bytes. The first byte (row 1) is
00001111 . The second byte (row 2) is 10000110. The third byte is 10110111. And so on.
A byte is the basic unit of data in computers. Most computers process data in strings of 8 bits or some multiple
(16, 24, 32, and so on). Likewise, the memory stores data in strings of 8 bits or some multiple of 8 bits.
(1 X 24 )
+
- - -
(1 X 23 ) + (0 X 22 ) + (0 X 2 1)
+ (1 X 2°) = 16 + 8 + 0 + 0 +
25
Binary 11001 is therefore equivalent to decimal 25.
As another example, the byte 11001100 converts to decimal as follows:
(1 X 26 ) + (0 X 25 ) + (0 X 24 )
(1 X 23 ) + (1 X 22) + (0 X 2 1) + (0 X 2°)
(1 X 27)
+
+
= 128 + 64 + 0 + 0 + 8 + 4 + 0 + 0 = 204
So, binary 11001100 is equivalent to decimal 204.
1-5 BINARY-TO-DECIMAL
CONVERSION
Fast and Easy Conversion
You already know how to count to 15 using binary numbers.
The next thing to learn is how to convert larger binary numbers to their decimal equivalents.
I I I I I I I
0
5
10
4
103
102
3
10
4
1
10°
24
23
0
0
22
21
20
(b)
(a)
Here's a streamlined way to convert a binary number to its decimal equivalent:
1.
2.
3.
4.
Fig. 1-5 (a) Decimal weights; (b) binary weights.
For instance, binary 1101 converts to decimal as follows:
2.
The decimal number system is an example of positional notation; each digit position has a weight or value. With decimal numbers the weights are units, tens, hundreds, thousands, and so on. The sum of all digits multiplied by their weights gives the total amount being represented.
For instance, Fig. l-5a illustrates a decimal odometer.
Below each digit is its weight. The digit on the right has a weight of 10° (units), the second digit has a weight of 10 1
(tens), the third digit a weight of 10 2 (hundreds), and so forth. The sum of all units multiplied by their weights is
X
104 )
+ (7
+ (4
X
X
0
1.
Decimal Weights
(5
Write the binary number.
Write the weights 1, 2, 4, 8,
. , under the binary digits. Cross out any weight under a 0.
Add the remaining weights.
103 ) + (0 X 102 ) + (3 X 10 1)
10°) = 50,000 + 7000 + 0 + 30
= 57,034
+4
8
3. 8
4.
8
4
2
4
0
+4 +0 + 1
=
(Write binary number)
(Write weights)
(Cross out weights)
(Add weights)
13
You can compress the steps even further:
1
(Step 1)
(Steps 2 to 4)
1 0
8 4
~
1~13
As another example, here's the conversion of binary
Ill 0101 in compressed form:
1
1
64
32
1
16
0
1 0
~
4
~
Base or Radix
Binary Weights
Positional notation is also used with binary numbers because each digit position has a weight. Since only two digits are used, the weights are powers of 2 instead of 10. As shown in the binary odometer of Fig. l-5b, these weights are 2°
(units), 2 1 (twos), 22 (fours), 23 (eights), and 24 (sixteens).
If longer binary numbers are involved, the weights continue in ascending powers of 2.
The decimal equivalent of a binary number equals the sum of all binary digits multiplied by their weights. For instance, the binary reading of Fig. l-5b has a decimal equivalent of
6
Digital Computer Electronics
The base or radix of a number system equals the number of digits it has. Decimal numbers have a base of 10 because digits 0 through 9 are used. Binary numbers have a base of 2 because only the digits 0 and 1 are used. (In terms of an odometer, the base or radix is the number of digits on each wheel.)
A subscript attached to a number indicates the base of the number. 100 2 means binary 100. On the other hand,
100 10 stands for decimal 100. Subscripts help clarify equations where binary and decimal numbers are mixed. For instance, the last two examples of binary-to-decimal conversion can be written like this:
11012 = 1310
11101012 = 11710
Microcomputer
What is inside a computer? What is a microprocessor? What is a microcomputer?
As the name implies, a microcomputer is a small computer.
More specifically, a microcomputer is a computer that uses a microprocessor for its CPU. The typical microcomputer has three kinds of chips: microprocessor (usually one chip), memory (several chips), and l/0 (one or more chips).
If a small memory is acceptable, a manufacturer can fabricate all computer circuits on a single chip. For instance, the 8048 from Intel Corporation is a one-chip microcomputer with an 8-bit CPU, 1,088 bytes of memory, and 27 l/0 lines. Computer
Powers of 2
The five main sections of a computer are input, memory, arithmetic and logic, control, and output. Here is a brief description of each.
Input This consists of all the circuits needed to get programs and data into the computer. In some computers the input section includes a typewriter keyboard that converts letters and numbers into strings of binary data.
Memory This stores the program and data before the computer run begins. It also can store partial solutions during a computer run, similar to the way we use a scratchpad while working out a problem.
Control This is the computer's center of gravity, analogous to the conscious part of the mind. The control section directs the operation of all other sections. Like the conductor of an orchestra, it tells the other sections what to do and when to do it.
Arithmetic and logic This is the number-crunching section of the machine. It can also make logical decisions.
With control telling it what to do and with memory feeding it data, the arithmetic-logic unit (ALU) grinds out answers to number and logic problems.
Output This passes answers and other processed data to the outside world. The output section usually includes a video display to allow the user to see the processed data.
Microprocessor design started with 4-bit devices, then evolved to 8- and 16-bit devices. In our later discussions of microprocessors, powers of 2 keep coming up because of the binary nature of computers. For this reason, you should study Table 1-3. It lists the powers of 2 encountered in microcomputer analysis. As shown, the abbreviation K stands for 1,024 (approximately 1,000). t Therefore, 1K means I ,024, 2K stands for 2,048, 4K for 4,096, and so on. Most personal microcomputers have 640K (or greater) memories that can store 655,360 bytes (or more).
In this book we will use subscripts when necessary for clarity. 1-6 MICROPROCESSORS
Microprocessor
The control section and the ALU are often combined physically into a single unit called the central processing unit (CPU). Furthermore, it's convenient to combine the input and output sections into a single unit called the inputoutput (110) unit. In earlier computers, the CPU, memory, and 1/0 unit filled an entire room.
With the advent of integrated circuits, the CPU, memory, and 1/0 unit have shrunk dramatically. Nowadays the CPU can be fabricated on a single semiconductor chip called a microprocessor. In other words, a microprocessor is nothing more than a CPU on a chip.
Likewise, the l/0 circuits and memory can be fabricated on chips. In this way, the computer circuits that once filled a room now fit on a few chips.
TABLE 1-3. POWERS OF 2
Powers of 2
Decimal equivalent
Abbreviation
20
2'
22
23
24
25
26
27
28
29
210
2"
212
213
2'4
2'5
2'6
2
4
8
16
32
64
128
256
512
1,024
2,048
4,096
8,192
16,384
32,768
65,536
1K
2K
4K
8K
16K
32K
64K
t The abbreviations lK, 2K, and so on, became established before K- for kilo- was in common use. Retaining the capital K serves as a useful reminder that K only approximates 1,000.
Chapter 1
Number Systems and Codes
7
1-7 DECIMAL-TO-BINARY
CONVERSION
Next, you need to know how to convert from decimal to binary. After you know how it's done, you will be able to understand how circuits can be built to convert decimal numbers into binary numbers.
Double-Dabble
Double-dabble is a way of converting any decimal number to its binary equivalent. It requires successive division by
2, writing down each quotient and its remainder. The remainders are the binary equivalent of the decimal number.
The only way to understand the method is to go through an example, step by step.
Here is how to convert decimal13 to its binary equivalent.
Step 1. Divide 13 by 2, writing your work like this:
In this final division, 2 does not divide into 1; therefore,
the quotient is 0 with a remainder of 1.
Whenever you arrive at a quotient of 0 with a remainder of 1, the conversion is finished. The remainders when read downward give the binary equivalent. In this example, binary 1101 is equivalent to decimal 13.
Double-dabble works with any decimal number. Progressively divide by 2, writing each quotient and its remainder. When you reach a quotient of 0 and a remainder of 1, you are finished; the remainders read downward are the binary equivalent of the decimal number.
Streamlined Double-Dabble
There's no need to keep writing down 2 before each division because you're always dividing by 2. From now on, here's how to show the conversion of decimal 13 to its binary equivalent: 1 ~ (first remainder)
6
The quotient is 6 with a remainder of 1.
Step 2. Divide 6 by 2 to get
3
0
~
(second remainder)
EXAMPLE
1-4
Convert decimal 23 to binary.
This division gives 3 with a remainder of 0.
Step 3. Again you divide by 2:
1 ~ (third remainder)
SOLUTION
The first step in the conversion looks like this:
11
2) 23
After all divisions, the finished work looks like this:
Here you get a quotient of I and a remainder of 1.
Step 4. One more division by 2 gives
0
Read down This says that binary 10111 is equivalent to decimal 23.
8
Digital Computer Electronics
1-8 HEXADECIMAL NUMBERS
Hexadecimal numbers are extensively used in microprocessor work. To begin with, they are much shorter than binary numbers. This makes them easy to write and remember. Furthermore, you can mentally convert them to binary form whenever necessary.
An Unusual Odometer
Hexadecimal means 16. The hexadecimal number system has a base or radix of 16. This means that it uses 16 digits to represent all numbers. The digits are 0 through 9, and
A through F as follows: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B,
C, D, E, and F. Hexadecimal numbers are strings of these digits like 8A5, 4CF7, and EC58.
An easy way to understand hexadecimal numbers is to visualize a hexadecimal odometer. Each wheel has 16 digits on its circumference. As it turns, it displays 0 through 9 as before. But then, instead of resetting, it goes on to display A, B, C, D, E, and F.
The idea of reset and carry applies to a hexadecimal odometer. When a wheel turns from F back to 0, it forces the next higher wheel to advance by 1. In other words, when a wheel runs out of hexadecimal digits, it resets and carries. If used in a car, a hexadecimal odometer would count as follows. When the car is new, the odometer shows all
Os:
0000
(zero)
The next 15 miles produce these readings: 0011, 0012,
0013, 0014, 0015, 0016, 0017, 0018, 0019, 001A, OOlB,
OOlC, OOlD, 001E, and OOlF. Once again, the least significant wheel has run out of digits. So, the next mile results in a reset-and-carry:
0020
(thirty-two)
Subsequent readings are 0021, 0022, 0023, 0024, 0025,
0026,0027,0028,0029, 002A, 002B, 002C, 002D, 002E, and 002F.
You should have the idea by now. Each mile advances the least significant wheel by 1. When this wheel runs out of hexadecimal digits, it resets and carries. And so on for the other wheels. For instance, if the odometer reading is
835F
the next reading is 8360. As another example, given
5FFF
the next hexadecimal number is 6000.
Equivalences
Table 1-4 shows the equivalences between hexadecimal, binary, and decimal digits. Memorize this table. It's essential that you be able to convert instantly from one system to another. The next 9 miles produce readings of
0001
0002
0003
0004
0005
0006
0007
0008
0009
(one)
(two)
(three)
(four)
(five)
(six)
(seven)
(eight)
(nine)
The next 6 miles give
OOOA
OOOB
OOOC
OOOD
OOOE
OOOF
(ten)
(eleven)
(twelve)
(thirteen)
(fourteen)
(fifteen)
At this point the least significant wheel has run out of digits. Therefore, the next mile forces a reset-and-carry to get 0010
(sixteen)
TABLE 1-4. EQUIVALENCES
Hexadecimal
Binary
Decimal
0
1
2
3
4
5
6
7
8
9
A
B
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
c
D
E
F
Chapter 1
Number Systems and Codes
9
1-9 HEXADECIMAL-BINARY
CONVERSIONS
EXAMPLE 1-5
Solve the following equation for x:
After you know the equivalences of Table 1-4, you can mentally convert any hexadecimal string to its binary equivalent and vice versa.
SOLUTION
Hexadecimal to Binary
To convert a hexadecimal number to a binary number, convert each hexadecimal digit to its 4-bit equivalent, using
Table 1-4. For instance, here's how 9AF converts to binary:
9
~
1001
A
~
1010
F
~
1111
As another example, C5E2 converts like this:
c
5
~
0101
~
1100
E
~
1110
2
~
0010
Incidentally, for easy reading it's common practice to leave a space between the 4-bit strings. For example, instead of writing C5E2 16
=
x 16 = 1111111111111111 2
This is the same as asking for the hexadecimal equivalent of binary 1111 1111 1111 1111. Since hexadecimal F is equivalent to 1111, x = FFFF. Therefore,
FFFF 16
EXAMPLE
=
1-6
As mentioned earlier, the memory contains thousands of registers (core or semiconductor) that store the program and data needed for a computer run. These memory registers are known as memory locations. A typical microcomputer may have up to 65,536 memory locations, each storing 1 byte. Suppose the first 16 memory locations contain these bytes: 0011
1100
0101
0010
1111
0010
1101
0100
0111
1100
1000
0010
0010
0011
0011
0001
1100010111100010 2
we can write
C5E2 16
=
1100 0101 1110 0010 2
Binary to Hexadecimal
To convert in the opposite direction, from binary to hexadecimal, you again use Table 1-4. Here are two examples. The byte 1000 1100 converts as follows:
1000
~
8
1100
~
1111 1111 1111 1111 2
1100
1101
0111
1000
0001
1010
0100
0000
0111
0011
0100
1000
0001
1010
1110
1111
Convert these bytes to their hexadecimal equivalents.
c
SOLUTION
The 16-bit number 1110 1000 1101 0110 converts like this:
Here are the stored bytes and their hexadecimal equivalents:
1110
~
E
1000
~
8
1101
~
D
0110
~
6
In both these conversions, we start with a binary number and wind up with the equivalent hexadecimal number.
I 0
Digital Computer Electronics
Memory Contents
0011 1100
11001101
0101 0111
0010 1000
1111 0001
Hex Equivalents
3C
CD
57
28
F1
0010 1010
1101 0100
0100 0000
0111 0111
11000011
1000 0100
0010 1000
0010 0001
0011 1010
0011 1110
0001 1111
2A
D4
40
1100
0001
0101
0100
0010
1111
77
C3
84
28
21
3A
3E
lF
What's the point of this example? When talking about the contents of a computer memory, we can use either binary numbers or hexadecimal numbers. For instance, we can say that the first memory location contains 0011 1100, or we can say that it contains 3C. Either string gives the same information. But notice how much easier it is to say, write, and think 3C than it is to say, write, and think 0011
1100. In other words, hexadecimal strings are much easier for people to work with. This is why everybody working with microprocessors uses hexadecimal notation to represent particular bytes.
What we have just done is known as chunking, replacing longer strings of data with shorter ones. At the first memory location we chunk the digits 0011 1100 into 3C. At the second memory location we chunk the digits 1100 1101 into CD, and so on.
0011
1001
1010
1101
1100
1000
The first memory location stores the byte 1010 0 Ill, the second memory location stores the byte 0010 1000, and so on. This example emphasizes a widespread industrial practice. Microcomputers are programmed to display chunked data, often hexadecimal. The user is expected to know hexadecimal-binary conversions. In other words, a computer manufacturer assumes that you know that A7 represents
10 10 0111 , 28 stands for 00 10 1000, and so on.
One more point. Notice that each memory location in this example stores 1 byte. This is typical of first-generation microcomputers because they use 8-bit microprocessors.
1-10 HEXADECIMAL-TO-DECIMAL
CONVERSION
You often need to convert a hexadecimal number to its decimal equivalent. This section discusses methods for doing it.
Hexadecimal to Binary to Decimal
EXAMPLE
1-7
The typical microcomputer has a typewriter keyboard that allows you to enter programs and data; a video screen displays answers and other information.
Suppose the video screen of a microcomputer displays the hexadecimal contents of the first eight memory locations as One way to convert from hexadecimal to decimal is the two-step method of converting from hexadecimal to binary and then from binary to decimal. For instance, here's how to convert hexadecimal 3C to its decimal equivalent.
Step 1. Convert 3C to its binary equivalent:
A7
28
C3
c
3
t
t
0011
1100
Step 2. Convert 0011 1100 to its decimal equivalent:
19
SA
4D
2C
F8
0
0
J.28' M
1
32
16
1 1 0
8 4 ~
0
~
-7
60
Therefore, decimal 60 is equivalent to hexadecimal 3C. As an equation,
What are the binary contents of the memory locations?
SOLUTION
Positional-Notation Method
Convert from hexadecimal to binary to get
10100111
0010 1000
Positional notation is also used with hexadecimal numbers because each digit position has a weight. Since 16 digits are used, the weights are the powers of 16. As shown in
Chapter 1
Number Systems and Codes
11
---
------------------
I I I I I
F
1Eil
8
162
6
E
161
1~
Fig. 1-6 Hexadecimal weights.
the hexadecimal odometer of Fig. 1-6, the weights are 16°,
161, 162 , and 16 3 . If longer hexadecimal numbers are involved, the weights continue in ascending powers of 16.
The decimal equivalent of a hexadecimal string equals the sum of all hexadecimal digits multiplied by their weights.
(In processing hexadecimal digits A through F, use 10 through 15.) For instance, the hexadecimal reading of Fig.
1-6 has a decimal equivalent of
(F
16 3 ) + (8 X 162 ) + (E X 16 1) + (6
= (15 X 16 3) + (8 X 162 ) + (14 X 16 1)
= 61,440 + 2,048 + 224 + 6
= 63,718
X
+
16°)
(6 X 16°)
3C
CD
0002
57
0003
28
A 64K memory has 65,536 hexadecimal addresses from
0000 to FFFF. The equivalent binary addresses are from
to
1111 1111 1111 1111
The first 8 bits are called the upper byte (VB); the second
8 bits are the lower byte (LB). If you have to do a lot of binary-hexadecimal-decimal conversions, use the table of equivalents in Appendix 2, which shows all the values for a 64 K memory.
Appendix 2 has four headings: binary, hexadecimal, UB decimal, and LB decimal. Given a 16-bit address, you convert the upper byte to its decimal equivalent (UB decimal), the lower byte to its decimal equivalent (LB decimal), and then add the two decimal equivalents. For instance, suppose you want to convert
63,71810
0001
Table of Binary-Hexadecimal-Decimal
Equivalents
0000 0000 0000 0000
X
In other words,
0000
the people living in the house. Figure 1-7a emphasizes the point. At address 0000 the stored contents are 3C (equivalent to 0011 1100). At address 0001 the stored contents are CD, at address 0002 the stored contents are 57, and so on.
Figure 1-7b shows how to visualize a 64K memory. The first address is 0000, and the last is FFFF.
0000
0004
F1
0005
0006
2A
04
0007
40
16
65,536
0008
77
locations
locations
0009
C3
OOOA
84
0008
28
oooc
21
0000
3A
OOOE
3E
OOOF
1F
1101 0111 1010 0010 to its decimal equivalent. The upper byte is 1101 0111, or hexadecimal D7; the lower byte is 1010 0010, or A2. Using
Appendix 2, find D7 and its UB decimal equivalent
D7
55,040
Next, find A2 and its LB decimal equivalent
FFFF
(a)
A2
162
Add the UB and LB decimal equivalents to get
55,040
Memory Locations and Addresses
If a certain microcomputer has 64K memory, meaning
65,536 memory locations, each is able to store 1 byte. The different memory locations are identified by hexadecimal numbers called addresses. For instance, Fig. l-7a shows the first 16 memory locations; their addresses are from 0000 to OOOF.
The address of a memory location is different from its stored contents, just as a house address is different from
Digital Computer Electronics
~
(b)
Fig. 1-7 (a) First 16 words in memory; (b) 64K memory.
12
~
+ 162
=
55,202
This is the decimal equivalent of hexadecimal D7 A2 or binary 1101 0111 1010 0010.
Once familiar with Appendix 2, you will find it enormously helpful. It is faster, more accurate, and less tiring than other methods. The only calculation required is adding the UB and LB decimal, easily done mentally, with pencil and paper, or if necessary, on a calculator. Furthermore, if you are interested in converting only the lower byte, no calculation is required, as shown in the next example.
EXAMPLE
1-8
EXAMPLE
1-9
Convert hexadecimal 7E to its decimal equivalent.
Convert decimal 141 to hexadecimal.
SOLUTION
SOLUTION
When converting only a single byte, all you are dealing with is the lower byte. With Appendix 2, look up 7E and its LB decimal equivalent to get
Whenever the decimal number is between 0 and 255, all you have to do is look up the decimal number and its hexadecimal equivalent. With Appendix 2, you can see at a glance that
7E
~
126
8D
In other words, Appendix 2 can be used to convert single bytes to their decimal equivalents (LB decimal) or double bytes to their decimal equivalents (UB decimal + LB decimal). 1-11 DECIMAL-TO-HEXADECIMAL
CONVERSION
One way to perform decimal-to-hexadecimal conversion is to go from decimal to binary then to hexadecimal. Another way is hex-dabble. The idea is to divide successively by
16, writing down the remainders. (Hex -dabble is like doubledabble except that 16 is used for the divisor instead of 2.)
Here's an example of how to convert decimal 2,479 into hexadecimal form. The first division is
154
15
EXAMPLE
141
1-10
Convert decimal 36,020 to its hexadecimal equivalent.
SOLUTION
If the decimal number is between 256 and 65,535, you need to proceed as follows. First, locate the largest UB decimal that is less than 36,020. In Appendix 2, the largest
UB decimal is
UB decimal
=
35,840
which has a hexadecimal equivalent of
F
8C
16 ) 2,479
~
~
35,840
This is the upper byte.
Next, subtract the UB decimal from the original decimal number: The next step is
9
10
A
15
F
36,020 - 35,840 = 180
The difference 180 has a hexadecimal equivalent
B4
The final step is
Read
down
0
9 9
)9
10
A
) 154
15
F
~
180
This is the lower byte.
By combining the upper and lower bytes, we get the complete answer: 8CB4. This is the hexadecimal equivalent of 36,020.
After a little practice, you will find Appendix 2 to be one of the fastest methods of decimal-hexadecimal conversion.
16 ) 2,479
Notice how similar hex-dabble is to double-dabble. Also, remainders greater than 9 have to be changed to hexadecimal digits (10 becomes A, 15 becomes F, etc.).
If you prefer, use Appendix 2 to look up the decimalhexadecimal equivalents. The next two examples show how. 1-12 BCD NUMBERS
A nibble is a string of 4 bits. Binary-coded-decimal (BCD) numbers express each decimal digit as a nibble. For instance, decimal 2,945 converts to a BCD number as follows:
Chapter 1
Number Systems and Codes
13
2
9
4
5
t
t
t
t
0010
1001
0100
0101
As you see, each decimal digit is coded as a nibble.
Here's another example: 9,863 10 converts like this:
9
~
1001
8
~
1000
6
~
0110
3
~
0011
Therefore, 1001 1000 0110 0011 is the BCD equivalent of
9,86310.
The reverse conversion is similar. For instance, 0010
1000 0111 0100 converts as follows:
0010
~
2
1000
~
8
0111
~
7
0100
~
4
Applications
BCD numbers are useful wherever decimal information is transferred into or out of a digital system. The circuits inside pocket calculators, for example, can process BCD numbers because you enter decimal numbers through the keyboard and see decimal answers on the LED or liquidcrystal display. Other examples of BCD systems are electronic counters, digital voltmeters, and digital clocks; their circuits can work with BCD numbers.
BCD Computers
BCD numbers have limited value in computers. A few early computers processed BCD numbers but were slower and more complicated than binary computers. As previously mentioned, a computer is more than a number cruncher because it must handle names and other nonnumeric data.
In other words, a modem computer must be able to process alphanumerics (alphabet letters, numbers, and other symbols). This why modem computers have CPUs that process binary numbers rather than BCD numbers.
Comparison of Number Systems
Table 1-5 shows the four number systems we have discussed.
Each number system uses strings of digits to represent quantity. Above 9, equivalent strings appear different. For instance, decimal string 128, hexadecimal string 80, binary string 1000 0000, and BCD string 0001 0010 1000 are equivalent because they represent the same number of pebbles. Machines have to use long strings of binary or BCD numbers, but people prefer to chunk the data in either decimal or hexadecimal form. As long as we know how to
14
Digital Computer Electronics
TABLE 1-5. NUMBER SYSTEMS
Decimal Hexadecimal
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
64
128
255
0
1
2
3
4
5
6
7
8
9
A
B
c
D
E
F
10
20
40
80
FF
Binary
0000 0000
0000 0001
0000 0010
0000 0011
0000 0100
0000 0101
0000 0110
0000 0111
0000 1000
0000 1001
0000 1010
0000 1011
0000 1100
0000 1101
00001110
0000 1111
0001 0000
0010 0000
0100 0000
1000 0000
1111 1111
BCD
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0001
0000 0001
0000 0001
0000 0001
0000 0001
0000 0001
0000 0001
0000 0011
0000 0110
000 1 00 10
0010 0101
0000
0001
0010
00 11
0100
0101
0110
0 Ill
1000
1001
0000
000 1
0010
0011
0100
0101
0 110
0010
0100
1000
0101
convert from one number system to the next, we can always get back to the ultimate meaning, which is the number of pebbles being represented.
1-13 THE ASCII CODE
To get information into and out of a computer, we need to use numbers, letters, and other symbols. This implies some kind of alphanumeric code for the 1/0 unit of a computer.
At one time, every manufacturer had a different code, which led to all kinds of confusion. Eventually, industry settled on an input-output code known as the American
Standard Code for Information Interchange (abbreviated
ASCII). This code allows manufacturers to standardize
110 hardware such as keyboards, printers, video displays, and so on.
The ASCII (pronounced ask'-ee) code is a 7-bit code whose format (arrangement) is
where each X is a 0 or a 1. For instance, the letter A is coded as
1000001
Sometimes, a space is inserted for easier reading:
100 0001
TABLE 1-6. THE ASCII CODE
X3X2X1X0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
More examples are
110 0010
1100011
1100100
X6XsX4
010
011
100
101
SP
0
p
Q
R
"
#
$
%
&
2
@
A
B
3
c
s
4
D
E
F
G
H
I
T
5
6
7
8
9
*
u v w
X
y
z
J
+
K
<
>
?
L
M
N
0
110 a b c d e f g h
111 p q r s
X
j k 010 0000
(space)
1-11
With an ASCII keyboard, each keystroke produces the
ASCII equivalent of the designated character. Suppose you type 0
(A)
PRINT X
What is the output of an ASCII keyboard?
SOLUTION
Table 1-6 includes the ASCII code for lowercase letters.
The letter a is coded as
110 0001
($)
(+)
(=)
In Table 1-6, SP stands for space (blank). Hitting the space bar of an ASCII keyboard sends this into a microcomputer:
EXAMPLE
Table 1-6 shows the ASCII code. Read the table the same as a graph. For instance, the letter A has an X 6X5X 4 of 100 and an X 3X 2X 1X 0 of 0001. Therefore, its ASCII code is
100 0001
010 0100
0101011
0111101
z
m n (d)
and so on.
Also look at the punctuation and mathematical symbols.
Some examples are
u v w y (b)
(c)
P (101 0000), R (101 0010), I (100 1001), N (100 1110),
T (101 0100), space (010 0000), X (101 1000).
(a)
GLOSSARY address Each memory location has an address, analogous to a house address. Using addresses, we can tell the computer where desired data is stored. alphanumeric Letters, numbers, and other symbols. base The number of digits (basic symbols) in a number system. Decimal has a base of 10, binary a base of 2, and hexadecimal a base of 16. Also called the radix. bit An abbreviation for binary digit. byte A string of 8 bits. The byte is the basic unit of binary information. Most computers process data with a length of
8 bits or some multiple of 8 bits. central processing unit The control section and the arithmetic-logic section. Abbreviated CPU. chip An integrated circuit. chunking Replacing a longer string by a shorter one. data Names, numbers, and any other information needed to solve a problem. digital Pertains to anything in the form of digits, for example, digital data.
hardware The electronic, magnetic, and mechanical devices used in a computer. hexadecimal A number system with a base of 16. Hexadecimal numbers are used in microprocessor work. input-output Abbreviated 110. The input and output sections of a computer are often lumped into one unit known as the 1/0 unit. microcomputer A computer that uses a microprocessor for its central processing unit (CPU). microprocessor A CPU on a chip. It contains the control and arithmetic-logic sections. Sometimes abbreviated MPU
(microprocessor unit). nibble A string of 4 bits. Half of a byte. program A sequence of instructions that tells the computer how to process the data. Also known as software. register A group of electronic, magnetic, or mechanical devices that store digital data. software Programs. string A group of digits or other symbols.
Chapter 1 Number Systems and Codes
15
SELF-TESTING REVIEW
Read each of the following and provide the missing words.
Answers appear at the beginning of the next question.
1.
2.
3.
4.
5.
6.
Binary means
. Binary numbers have a base of 2. The digits used in a binary number system are and - - - (two; 0, 1) Names, numbers, and other information needed to solve a problem are called _ _ __
The
is a sequence of instructions that tells the computer how to process the data.
(data, program) Computer ICs work reliably because they are based on design. When a transistor is cut off or saturated, transistor
_ _ _ _ have almost no effect.
(two-state, variations) A is a group of devices that store digital data. is an abbreviation for binary digit. A byte is a string of
_ _ _ _ bits.
(register, Bit, 8) The control and arithmetic-logic
(CPU). A microsections are called the processor is a CPU on a chip. A microcomputer is a computer that uses a for its CPU.
(central processing unit, microprocessor) The abbreviation K indicates units of approximately 1 ,000 or precisely 1,024. Therefore, 1K means 1,024, 2K means 2,048, 4K means
, and 64K means _ _ __
(4,096, 65,536) The hexadecimal number system is widely used in analyzing and programming - - The hexadecimal digits are 0 to 9 and A to - - The main advantage of hexadecimal numbers is the ease of conversion from hexadecimal to - - - and vice versa.
8. (microprocessors, F, binary) A typical microcomputer may have up to 65,536 registers in its memory. Each of these registers, usually called a---· stores 1 byte. Such a memory is specified as a 64kilobyte memory, or simply a memory. 9. (memory location, 64K) Binary-coded-decimal
(BCD) numbers express each decimal digit as a - - ·
BCD numbers are useful whenever information is transferred into or out of a digital system. Equipment using BCD numbers incl~d~s pocket calculators, electronic counters, and digital voltmeters. 10. (nibble, decimal) The ASCII code is a 7-bit code for (letters, numbers, and other symbols).
11. (alphanumerics) With the typical microcomputer, you enter the program and data with typewriter keyboard that converts each character into ASCII code. 7.
PROBLEMS
1-1.
1-2.
1-3.
1-4.
How many bytes are there in each of these numbers?
a. 1100 0101
b. 1011 1001 0110 1110
c. 1111 1011 0111 0100 1010
What are the equivalent decimal numbers for each of the following binary numbers: 10, 110, 111,
1011, llOO, and 1110?
What is the base for each of these numbers?
a. 348 10
b. 1100 01012
c. 23125
d. F4C3I6
Write the equation
2
1-5.
1-6.
16
+
2
=;
4
using binary numbers.
What is the decimal equivalent of 2 10 ? What does
4K represent? Express 8,192 inK units.
A 4-bit register has output voltages of high-lowhigh-low. What is the binary number stored in the register? The decimal equivalent?
Digital Computer Electronics
oeoeooee
Fig. 1-8 An 8-bit LED display.
1-7.
1-8.
1-9.
Figure 1-8 shows an 8-bit LED display. A light circle means that a LED is ON (binary 1) and a dark circle means a LED is OFF (binary 0). What is the binary number being displayed? The decimal equivalent?
Convert the following binary numbers to decimal numbers: a. 00111
b. 11001
c. 10ll0
d. 11110
Solve the following equation for x:
x 10
1-10.
""
110010012
An 8-bit transistor register has this output: low-high-low-high-low-high-low-high What is the equivalent decimal number being stored? Fig. 1-9 An 8-bit core register.
1-11.
In Fig. 1-9 clockwise flux stands for binary 1 and counterclockwise flux for binary 0. What is the binary number stored in the 8-bit core register?
Convert this byte to an equivalent decimal number. r-----------~----------~----------~~--------~~~+5V
Fig. 1-10 A 5-bit switch register.
'_,'
1-12.
1-13.
1-14.
1-15.
1-16.
1-17.
1-18.
1-19.
1-20.
Figure 1-10 shows a 5-bit switch register. By opening and closing the switches you can set up different binary numbers. As usual, high output voltage stands for binary 1 and low output voltage for binary 0. What is the binary number stored in the switch register? The equivalent decimal number?
Convert decimal 56 to its binary equivalent.
Convert 72 10 to a binary number.
An 8-bit transistor register stores decimal 150.
What is the binary output of the register?
How would you set the switches of Fig. 1-10 to get a decimal output of 27?
A hexadecimal odometer displays F52A. What are the next six readings?
The reading on a hexadecimal odometer is 27FF.
What is the next reading? Miles later, you see a reading of 8AFC. What are the next six readings?
Convert each of the following hexadecimal numbers to binary:
a. FF
b. ABC
c. CD42
d. F329
Convert each of these binary numbers to an equivalent hexadecimal number:
a. 1110 1000
b. 1100 1011
c. 1010 1111 0110
d. 1000 1011 1101 0110
1-21.
Here is a program written for the 8085 microprocessor:
Address
Hex Contents
2000
2001
2002
2003
2004
1-22.
1-23.
1-24.
1-25.
3E
OE
D3
20
76
Convert the hex contents to equivalent binary numbers. Convert each of these hexadecimal numbers to its decimal equivalent:
a. FF
b. A4
c. 9B
d. 3C
Convert the following hexadecimal numbers to their decimal equivalents:
a. OFFF
b. 3FFF
c. 7FE4
d. B3D8
A microcomputer has memory locations from
0000 to OFFF. Each memory location stores 1 byte. In decimal, how many bytes can the microcomputer store in its memory? How many kilobytes is this?
Suppose a microcomputer has memory locations from 0000 to 3FFF, each storing l byte. How
Chapter 1
Number Systems and Codes
17
1-26.
1-27.
1-28.
1-29.
1-30.
18
many bytes can the memory store? Express this in kilobytes. A microcomputer has a 32K memory. How many bytes does this represent? If 0000 stands for the first memory location, what is the hexadecimal notation for the last memory location?
If a microcomputer has a 64K memory, what are the hexadecimal notations for the first and last memory locations?
Convert the following decimal numbers to hexadecimal:
a. 4,095
b. 16,383
c. 32,767
d. 65,535
Convert each of the following decimal numbers to hexadecimal numbers:
a. 238
b. 7,547
c. 15,359
d. 47,285
How many nibbles are there in each of the following:
a. 10000111'
b. 1001 000,0 01QO ooi 1 . r c. 0~16'! 1oo 1 o111 oo io 01 '10 011 o
Digital Computer Electronics
.-,
· 1-31.
1-32.
1-33.
1-34.
If the numbers in Prob. 1-30 are BCD numbers, what are the equivalent decimal numbers?
What is the ASCII code for each of the following:
a. 7
b. w
c. f
d. y
Suppose you type LIST with an ASCII keyboard.
What is the binary output as you strike each letter? For each of the following rows, provide the missing numbers in the bases indicated.
Base 2
a.
b.
c.
200
3CD
125
1101 1110 1111
FFFF
f.
g.
Base 16
0100 0001
d.
e.
Base 10
2,000
=D-
2
GATES
For centuries mathematicians felt there was a connection between mathematics and logic, but no one before George
Boole could find this missing link. In 1854 he invented symbolic logic, known today as boolean algebra. Each variable in boolean algebra has either of two values: true or false. The original purpose of this two-state algebra was to solve logic problems.
Boolean algebra had no practical application until 1938, when Claude Shannon used it to analyze telephone switching circuits. He let the variables represent closed and open relays. In other words, Shannon came up with a new application for boolean algebra. Because of Shannon's work, engineers realized that boolean algebra could be applied to computer electronics.
This chapter introduces the gate, a circuit with one or more input signals but only one output signal. Gates are digital (two-state) circuits because the input and output signals are either low or high voltages. Gates are often called logic circuits because they can be analyzed with boolean algebra.
An inverter is also called a NOT gate because the output is not the same as the input. The output is sometimes called the complement (opposite) of the input.
+5V
1 kS1
{Jdc? 10
(0 or +5 V)
Fig. 2-1 Example of inverter design.
TABLE 2-2
TABLE 2-1
High
Low
Low
High
2-1 INVERTERS
An inverter is a gate with only one input signal and one output signal; the output state is always the opposite of the input state.
Transistor Inverter
Figure 2-1 shows a transistor inverter. This common-emitter amplifier switches between cutoff and saturation. When VrN is low (approximately 0 V), the transistor cuts off and VouT is high. On the other hand, a high VrN saturates the transistor, forcing VoUT to go low.
Table 2-1 summarizes the operation. A low input produces a high output, and a high input results in a low output.
Table 2-2 gives the same information in binary form; binary
0 stands for low voltage and binary 1 for high voltage.
0
0
IIIN
--<{>--
VOUT
(b)
VIN
-{::>o--C:>o-(c)
V OUT
IIIN--{:>-- VouT
(d)
Fig. 2-2 Logic symbols: (a) inverter; (b) another inverter symbol;
(c) double inverter; (d) buffer.
Inverter Symbol
Figure 2-2a is the symbol for an inverter of any design.
Sometimes a schematic diagram will use the alternative symbol shown in Fig. 2-2b; the bubble (small circle) is on
19
---------
the input side. Whenever you see either of these symbols,
remember that the output is the complement of the input.
Noninverter Symbol
If you cascade two inverters (Fig. 2-2c), you get a noninverting amplifier. Figure 2-2d is the symbol for a noninverting amplifier. Regardless of the circuit design, the action is always the same: a low input voltage produces a low output voltage, and a high input voltage results in a high output voltage.
The main use of noninverting amplifier is buffering
(isolating) two other circuits. More will be said about buffers in a later chapter.
EXAMPLE
2-1
A
8
c
6~btt
register
D
E
F
1
0
A
Fig. 2-4 A 2-input diode
Diode
OR
OR
gate.
Gate
Figure 2-4 shows one way to build an OR gate. If both inputs are low, the output is low. If either input is high, the diode with the high input conducts and the output is high. Because of the two inputs, we call this circuit a 2input OR gate.
Table 2-3 summarizes the action; binary 0 stands for low voltage and binary 1 for high voltage. Notice that one or more high inputs produce a high output; this is why the circuit is called an OR gate.
0
0
1
6bit register 0
0
o
1
(a)
"»---"
(b)
Fig. 2-5 A 3-input diode
OR
gate.
More than Two Inputs
Fig. 2-3 Example 2-1.
Figure 2-3a has an output, A to F, of 100101. Show how to complement each bit.
SOLUTION
Easy. Use an inverter on each signal line (Fig. 2-3b). The final output is now 011010.
A hex inverter is a commercially available IC containing six separate inverters. Given a 6-bit register like Fig. 2-3a, we can connect a hex inverter to complement each bit as shown in Fig. 2-3b.
One more point. In Fig. 2-3a the bits may represent a coded instruction, number, letter, etc. To convey this variety of meaning, a string of bits is often called a binary word or simply a word. In Fig. 2-3b the word 100101 is complemented to get the word 011010.
2-2 OR GATES
The OR gate has two or more input signals but only one output signal. If any input signal is high, the output signal is high.
20
Digital Computer Electronics
Figure 2-5 shows a 3-input OR gate. If all inputs are low, all diodes are off and the output is low. If 1 or more inputs are high, the output is high.
Table 2-4 summarizes the action. A table like this is called a truth table; it lists all the input possibilities and the corresponding outputs. When constructing a truth table, always list the input words in a binary progression as shown
(000, 001, 010, ... , 111); this guarantees that all input possibilities will be accounted for.
An OR gate can have as many inputs as desired; add one diode for each additional input. Six diodes result in a 6-
input OR gate, nine diodes in a 9-input OR gate. No matter how many inputs, the action of any OR gate is summarized like this: one or more high inputs produce a high output.
Bipolar transistors and MOSFETs can also be used to build OR gates. But no matter what devices are used, OR gates always produce a high output when one or more inputs are high. Figure 2-6 shows the logic symbols for
2-, 3-, and 4-input OR gates.
=D-(a)
(b)
(c)
Fig. 2-6 OR-gate symbols.
EXAMPLE
2-3
How many inputs words are in the truth table of an 8-input gate? Which input words produce a high output?
OR
SOLUTION
The input words are 0000 0000, 0000 000 1, . . . , 1111
1111. With the formula of the preceding example, the total number of input words is 2" = 28 = 256.
In any OR gate, 1 or more high inputs produce a high output. Therefore, the input word of 0000 0000 results in a low output; all other input words produce a high output.
EXAMPLE
EXAMPLE
2-2
+5
Show the truth table of a 4-input
OR
gate.
2-4
v
0
1
SOLUTION
2
Let Y stand for the output bit and A, B, C, D for input bits.
Then the truth table has input words of 0000, 0001, 0010,
... , 1111, as shown in Table 2-5. As expected, output Y is 0 for input word 0000; Y is 1 for all other input words.
As a check, the number of input words in a truth table always equals 2", where n is the number of input bits. A
2-input OR gate has a truth table with 22 or 4 input words; a 3-input OR gate has 23 or 8 input words; and a 4-input
OR gate has 24 or 16 input words.
3
4
5
6
7
8 _L_
...
9 _L_
TABLE 2-5. FOUR-INPUT
GATE
OR
A
B
c
D
y
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
0
y3
0
0
1
0
0
0
0
1
0
0
1
0
0
0
1
0
1
0
y2
Fig. 2-7 Decimal-to-binary encoder.
The switches of Fig. 2-7 are push-button switches like those of a pocket calculator. The bits out of the OR gates form a
4-bit word, designated Y3 Y2 Y 1Y0 • What does the circuit do? SOLUTION
Figure 2-7 is a decimal-to-binary encoder, a circuit that converts decimal to binary. For instance, when push button
3 is pressed, the Y 1 and Y0 OR gates have high inputs; therefore, the output word is
Chapter 2
Gates
21
If button 5 is keyed, the Y2 and Y 0
OR
gates have high
inputs and the output word becomes
When switch 9 is pressed,
Check the other input switches to convince yourself that the output word always equals the binary equivalent of the switch being pressed.
2-3 AND GATES
Table 2-6 summarizes the action. As usual, binary zero stands for low voltage and binary 1 for high voltage. As you see, A and B must be high to get a high output; this is why the circuit is called an AND gate.
+5
The AND gate has two or more input signals but only one output signal. All inputs must be high to get a high output.
+5
v
+5
v
v
c o-----too--___J
Fig. 2-9 A 3-input
-
y
AND
gate.
..,__._-{) y
More than Two Inputs
-
(a)
+5
+5
(b)
v
+5
v
+5
v
+5
v
v
y
(c)
(d)
Fig. 2-8 A 2-input AND gate. (a) circuit; (b) both inputs low; (c) I low input, I high; (d) both inputs high.
Diode AND Gate
Figure 2-8a shows one way to build an AND gate. In this circuit the inputs can be either low (ground) or high ( + 5
V). When both inputs are low (Fig. 2-Sb), both diodes conduct and pull the output down to a low voltage. If one of the inputs is low and the other high (Fig. 2-Sc), the diode with the low input conducts and this pulls the output down to a low voltage. The diode with the high input, on the other hand, is reverse-biased or cut off, symbolized by the dark shading in Fig. 2-Sc.
When both inputs are high (Fig. 2-Sd), both diodes are cut off. Since there is no current in the resistor, the supply voltage pulls the output up to a high voltage ( + 5 V).
22
Digital Computer Electronics
Figure 2-9 is a 3-input AND gate. If all inputs are low, all diodes conduct and pull the output down to a low voltage.
Even one conducting diode will pull the output down to a low voltage; therefore, the only way to get a high output is to have all inputs high. When all inputs are high, all diodes are nonconducting and the supply voltage pulls the output up to a high voltage.
Table 2-7 summarizes the 3-input AND gate. The output is 0 for all input words except 111. That is, all inputs must be high to get a high output.
AND gates can have as many inputs as desired; add one diode for each additional input. Eight diodes, for instance, result in an 8-input AND gate; sixteen diodes in a 16-input
TABLE 2-7. THREEINPUT AND GATE
A
B
c
y
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
For instance, when
(a)
ENABLE = 0
(b)
(c)
Fig. 2-10 AND-gate symbols.
AND gate. No matter how many inputs an AND gate has, the action can be summarized like this: All inputs must be high to get a high output.
Figure 2-10 shows the logic symbols for 2-, 3-, and 4input AND gates.
EXAMPLE
each AND gate has a low ENABLE input. No matter what the register contents, the output of each AND gate must be low. Therefore, the final word is
As you see, a low ENABLE blocks the register contents from the final output.
On the other hand, when
2-5
Describe the truth table of an 8-input
AND
ENABLE
gate.
=
the output of each AND gate depends on the data inputs (A,
B, C, ... ); a low data input results in a low output, and
SOLUTION
The input words are from 0000 0000 to 1111 1111, following the binary progression. The total number of input words is
a high data input in a high output. For example, if ABCDEF
100100, a high ENABLE gives
2" = 28 = 256
The first 255 input words produce a 0 output. Only the last word, 1111 1111, results in a 1 output. This is because all inputs must be high to get a high output.
In general, a high ENABLE transmits the register contents to the final output to get
ABCDEF
2-6
EXAMPLE
2-4 BOOLEAN ALGEBRA
6~bit
A
8
C
register
D
E
F
As mentioned earlier, Boole invented two-state algebra to solve logic problems. This new algebra had no practical use until Shannon applied it to telephone switching circuits.
Today boolean algebra is the backbone of computer circuit analysis and design.
Inversion Sign
Fig. 2-11 Using AND gates to block or transmit data.
The 6-bit register of Fig. 2-11 stores the word ABCDEF.
The ENABLE input can be low or high. What does the circuit do?
In boolean algebra a variable can be either a 0 or a 1. For digital circuits, this means that a signal voltage can be either low or high. Figure 2-12 is an example of a digital circuit because the input and output voltages are either low or high. Furthermore, because of the inversion, Y is always the complement of A.
SOLUTION
Fig. 2-12 Inverter.
One use of AND gates is to transmit data when certain conditions are satisfied. In Fig. 2-11 a low ENABLE blocks the register contents from the final output, but a high
ENABLE transmits the register contents.
A word equation for Fig. 2-12 is
Y
=
NOT
A
(2-1)
Chapter 2
----
Gates
23
-------------------------
If A is 0,
In boolean algebra the
Y =NOT 0
Y = NOT 1 = 0
In boolean algebra, the overbar stands for the NOT operation. This means that Eq. 2-1 can be written
Y=A
Y=A+B=O+O=O
If A
0 and B = 1,
Y
gate.
Sign
A word equation for Fig. 2-13 is
(2-3)
0 OR 0 = 0
because 0 comes out of an OR gate when both inputs are
Os.
As another example, if A = 0 and B = I,
Y
Fig. 2-14
AND
24
gate.
A word equation for Fig. 2-14 is
Y =A AND B
(2-5)
In boolean algebra the multiplication sign stands for the
AND operation. Therefore, Eq. 2-5 can be written
Y =A· B or simply
1'
Y
AND
Sign
Y = I OR 0
1 and B
0,
:=o--y
= 0 OR 1 = 1
because 1 comes out of an OR gate when either input is 1.
Similarly, if A = 1 and B = 0,
If A
1 = 1
because 1 ORed with 1 gives 1.
Don't let the new meaning of the + sign bother you.
There's nothing unusual about symbols having more than one meaning. For instance, "pot" may mean a cooking utensil, a flower container, the money wagered in a card game, a derivative of cannabis sativa and so forth; the intended meaning is clear from the sentence it's used in.
Similarly, the + sign may stand for ordinary addition or
OR addition; the intended meaning comes across in the way it's used. If we're talking about decimal numbers, + means ordinary addition, but when the discussion is about logic circuits, + stands for OR addition.
Given the inputs, you can solve for the output. For instance, if A = 0 and B = 0,
=
+
Y=A+B=l+l
because NOT 1 is 0.
Y
= 0
If both inputs are high,
Y=A=l=O
ORB
A+B
Y=A+B=l+O=l
because NOT 0 is 1. On the other hand, if A is I,
Y =A
=
because 0 ORed with 1 results in 1 . If A = 1 and B
Y=A=O=l
OR
(2-4)
Read this as '' Y equals A OR B.'' Equation 2-4 is the standard way to write the output of an OR gate.
Given the inputs, you can substitute and solve for the output. For instance, if A = 0 and B = 0,
(2-2)
Read this as '' Y equals NOT A'' or '' Y equals the complement of A." Equation 2-2 is the standard way to write the output of an inverter.
Using the equation is easy. Given the value of A, substitute and solve for Y. For instance, if A is 0,
OR
sign stands for the OR operation.
Y=A+B
On the other hand, if A is 1,
Fig. 2-13
+
In other words, Eq. 2-3 can be written
=
I OR 1
Digital Computer Electronics
y = AB
(2-6)
Read this as '' Y equals A AND B.'' Equation 2-6 is the standard way to write the output of an AND gate.
Given the inputs, you can substitute and solve for the output. For instance, if both inputs are low,
The distinction between italic and roman notation will become clearer when we get to computer analysis.
Y=AB=O·O=O
A final point. Positive logic means that I stands for the more positive of the two voltage levels. Negative logic means that 1 stands for the more negative of the two voltage levels. For instance, if the two voltage levels are 0 and -5
V, positive logic would have 1 stand for 0 V and 0 for - 5
V, whereas negative logic would have I stand for - 5 V and 0 for 0 V.
Ordinarily, people use positive logic with positive supply voltages and negative logic with negative supply voltages.
Throughout this book, we will be using positive logic.
because 0 ANDed with 0 gives 0. If A is low and B is high,
Y=AB=O·!=O
because 0 comes out of an AND gate if any input is 0. If A is 1 and B is 0,
Y=AB=l·O
0
When both inputs are high,
Positive and Negative Logic
EXAMPLE
2-7
Y=AB=l·l
because 1 ANDed with 1 gives 1.
(a)
Decision-Making Elements
The inverter, OR gate, and AND gate are often called decision-making elements because they can recognize some input words while disregarding others. A gate recognizes a word when its output is high; it disregards a word when its output is low. For example, the AND gate disregards all words with one or more Os; it recognizes only the word whose bits are all ls.
(b)
Fig. 2-15 Logic circuits.
What is the boolean equation for Fig. 2-15a? The output if both inputs are high?
SOLUTION
Notation
In later equations we need to distinguish between bits that are ANDed and bits that are part of a binary word. To do this we will use italic (slanted) letters (A, B, Y, etc.) for
ANDed bits and roman (upright) letters (A, B, Y, etc.) for bits that form a word.
For example, Y3Y2Y 1Y0 stands for the logical product
(ANDing) of Y 3 , Y2 , Y1 , and Y0 • If Y 3 = 1, Y2 = 0, Y1 =
0, and Y0 = 1, the product Y3 Y2 Y 1Y0 will reduce as follows:
Y 3 Y 2 Y I Y0 = 1 · 0 · 0 · 1 = 0
A is inverted before it reache~ the OR gate; therefore, the upper input to the OR gate is A. The final output is
Y=A+B
This is the boolean equation for Fig. 2-15a.
To find the output when both inputs are high, either of two approaches can be used. First, you can substitute directly into the foregoing equation and solve for Y
f\j· 1. ·r ' ,,
Y=A+B=l+l=O+l=I
In this case, the italic letters represent bits that are being
ANDed.
On the other hand, Y3 Y2 Y 1Y0 is our notation for a 4-bit word. With the Y values just given, we can write
Alternatively, you can analyze the operation of Fig. 2-15a like this. If both inputs are high, the inputs to the OR gate are 0 and 1. Now, 0 ORed with 1 gives 1. Therefore, the final output is high.
i}
In this equation, we are not dealing with bits that are
ANDed; instead, we are dealing with bits that are part of a word. EXAMPLE
2-8
What is the boolean equation for Fig. 2-15b? If both inputs are high, what is the output?
Chapter 2
Gates
25
TABLE 2-8. TRUTH TABLE
FOR Y = AB +CD
SOLUTION
The AND gate forms the logical product AB, which is inverted to get
Y=AB
Read this as '' Y equals NOT AB'' or '' Y equals the complement of AB. ''
If both inputs are high, direct substitution into the equation gives Y=AB=1·1=1=0
A
B
c
D
y
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
I
0
0
I
I
0
0
1
I
0
0
0
I
0
I
0
I
0
I
0
I
0
1
0
1
0
0
0
0
I
0
0
0
I
0
0
0
and
D
I
I
0
0
0
0
Note the order of operations: the ANDing is done first, then the inversion.
Instead of using the equation, you can analyze Fig.
2-15b as follows. If both inputs are high, the AND gate has a high output. Therefore, the final output is low.
EXAMPLE
1
1
2-9
A
CD is 1 when
8
y
c
c
=
I
D
Both products are Is when
(a)
A= I
B = 1
C=
D = I
and
y
Therefore, the final output is high when A and B are ls, when C and D are Is, or when all inputs are Is.
Table 2-8 summarizes the foregoing analysis. From this it's clear that the circuit recognizes these input words: 0011,
011I, 10II, 1100, 110I, 1I10, and 1111.
(b)
Fig. 2-16 Logic circuits.
What is the boolean equation for Fig. 2-16a? The truth table? Which input words does the circuit recognize?
EXAMPLE
2-10
Write the boolean equation for Fig. 2-I6b. If all inputs are high, what is the output?
SOLUTION
SOLUTION
The upper AND gate forms the logical product AB, and the lower AND gate gives CD. ORing these products results in
The OR gate forms the logical sum B
ANDed with A to get
+
C. This sum is
Y = AB +CD
Y = A(B
Read this as '' Y equals AB OR CD.''
Next, look at Fig. 2-l6a. The final output is high if the
OR gate has one or more high inputs. This happens when
AB is I, CD is I, or both are Is. In turn, AB is I when
A= I
26
and
B=I
Digital Computer Electronics
+
C)
(Parentheses indicate ANDing.)
One way to find the output when all inputs are high is to substitute and solve as follows:
Y = A(B
+
C) = 1(1
+
I)
I(I)
Alternatively, you can analyze Fig. 2-l6b like this. If all inputs are high, the OR gate has a high output; therefore, both inputs to the AND gate are high. Since all high inputs to an AND gate result in a high output, the final output is high. SOLUTION
Each AND gate forms the logical product of its input signals.
The inputs to the top AND gate are A, B, C and D; therefore,
Yo= ABCD
EXAMPLE
2-11
The inputs to the next means that
AND
gate are
A, B, C and
D; this
4-bit register
B
A
~~ c c
Y 1 = ABCD
D
~ ~ ~
Analyzing the remaining gates gives
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
'
\
./
I
I
I
~
J
\
EXAMPLE
= ABCD
= ABCD
= ABCD
= ABCD
=
ABCD
= ABCD
=
ABCD
= ABCD
2-12
What does the circuit of Fig. 2-17 do?
J
SOLUTION
'
J'
I
.
L
I
Fig. 2-17 A 1-of-10 decoder.
What is the boolean equation for each Y output in Fig.
2-17?
This is a binary-to-decimal decoder, a circuit that converts from binary to decimal. For instance, when the register contents are 0011, the Y3 AND gate has all high inputs; therefore, Y 3 is high. Furthermore, register contents ofOOll mean that all other AND gates have at least one low input.
As a result, all other AND gates have low outputs. (Analyze the circuit to convince yourself.)
If the register contents change to 0100, only the Y 4 AND gate has all high inputs; therefore, only Y 4 is high. If the register contents change to 0 Ill, Y7 is the only high output.
In general, the subscript of the high output equals the decimal equivalent of the binary number stored in the register. This is why the circuit is called a binary-to-decimal decoder. The circuit of this example is also called a 4-line-to-1 0line decoder because there are 4 input lines and 10 output lines. Another name for it is a 1-of-10 decoder because only 1 of 10 output lines has a high voltage.
GLOSSARY gate A logic circuit whose output is high only when all inputs are high.
AND
boolean algebra Originally known as symbolic logic, this modem algebra uses the set of numbers 0 and I. The
Chapter 2
Gates
27
operations
OR, AND, and NOT are sometimes called union, intersection, and inversion. Boolean algebra is ideally suited
to digital circuit analysis. complement The output of an inverter. gate A logic circuit with one or more input signals but only one output signal. inverter A gate with only 1 input and 1 output. The output is always the complement of the input. Also known as a
NOT gate. logic circuit A circuit whose input and output signals are
two-state, either low or high voltages. The basic logic circuits are OR, AND, and NOT gates.
OR gate A logic circuit with 2 or more inputs and only 1 output; 1 or more high inputs produce a high output. truth table A table that shows all input and output possibilities for a logic circuit. The input words are listed in binary progression. word A string of bits that represent a coded instruction or data.
SELF-TESTING REVIEW
Read each of the following and provide the missing words.
Answers appear at the beginning of the next question.
5.
1.
2.
3.
4.
A gate is a logic circuit with one or more input signals but only output signal. These signals are either or high.
(one, low) An inverter is a gate with only _ _ __ input; the output is always in the opposite state from the input. An inverter is also called a _ _ __ gate. Sometimes the output is referred to as the complement of the input.
(1, NOT) The OR gate has two or more input signals.
, the output is high. The
If any input is number of input words in a truth table always equals
_ _ _ _ , where n is the number of input bits.
(high, 2") The gate has two or more
6.
7.
input signals. All inputs must be high to get a high output. (AND) In boolean algebra, the overbar stands for the
NOT operation, the plus sign stands for the _ _ __ operation, and the times sign for the _ _ __ operation. (OR, AND) The inverter, OR gate, and AND gate are called decision-making elements because they can recognize some input while disregarding others. A gate recognizes a word when its output is
(words, high) A binary-to-decimal decoder is also called a 4-line-to--10-line decoder because it has 4 input lines and 10 output lines. Another name for it is the 1-of-1 0 decoder because only 1 of its 10 output lines is high at a time.
PROBLEMS
2-1.
2-2.
2-3.
2-4.
2-5.
2-6.
28
How many inputs signals can a gate have? How many output signals?
If you cascade seven inverters, does the overall circuit act like an inverter or noninverter?
Double inversion occurs when two inverters are cascaded. Does such a connection act like an inverter or noninverter?
The contents of the 6-bit register in Fig. 2-3b change to 101010. What is the decimal equivalent of the register contents? The decimal equivalent out of the hex inverter?
An OR gate has 6 inputs. How many input words are in its truth table? What is the only input word that produces a 0 output?
Figure 2-18 shows a hexadecimal encoder, a circuit that converts hexadecimal to binary. Pressing each push-button switch results in a different output word Y 3Y2Y 1Y0 • Starting with switch
0, what are the output words? (NOTE: The new symbol in Fig. 2-18 is another way to draw an OR gate. Digital Computer Electronics
2-7.
In Fig. 2-18 what switches would you press to produce 0011 1001 1100 1111
2-8.
2-9.
2-10.
(Work from left to right.)
What is the 4-bit output in Fig. 2-18 when switch
A is pressed? Switch 4? Switch E? Switch 6?
An AND gate has 7 inputs. How many input words are in its truth table? What is the only input word that produces a 1 output?
Visualize the register contents of Fig. 2-19 as the word A7A 6 • • • A0 , and the final output as the word Y7Y6 • • • Y0 . What is the output word for each of the following conditions:
a. A7 A6 • • • A0 = 1100 1010, ENABLE
0.
b. A7A6 • • • A0 = 0101 1101, ENABLE
1.
c. A7 A6 • • • A0 = 1111 0000, ENABLE
1.
d. A7 A6 • • • A0 = 1010 1010, ENABLE = 0.
+5
v
0
.____________________________________________
____L_
-;;;:
-
1
I
I
r
I
l
I
Yo
Fig. 2-18 Hexadecimal encoder.
8-bit register
(a)
~=D----f>r-
y
(b)
Fig. 2-19
Fig. 2-20
2-11.
2-13.
2-12.
The 8-bit register of Fig. 2-19 stores 59 10 . What is the decimal equivalent of the final output word if ENABLE = 0? If ENABLE
I?
Answer these questions:
a. What input words does a 6-input OR gate recognize? What word does it disregard?
b. What input word does an 8-input AND gate recognize? What words does it disregard?
2-14.
2-15.
What is the boolean equation for Fig. 2-20a? The output if both inputs are high?
If all inputs are high in Fig. 2-20b, what is the output? The boolean equation for the circuit?
What is the only ABC input word the circuit recognizes? If you constructed the truth table for Fig. 2-20b, how many input words would it contain?
Chapter 2
Gates
29
A
y
l nstruct1on reyister
8
115
(a)
114
113
R1 l7 ~
A
c
...
lo
7
~
y
8
112
LOA
ADD
c
~
(b)
~
Fig. 2-21
D-
~
A
8
c
D-
y
~
D
E
SUB
STA
LOB
LOX
JMP
JAM
F
(a)
D- D~
(b)
Fig. 2-22
D-
~
D-
JAZ
JIM
JIZ
JMS
DSZ
ISZ
.....--
y
~
MIX
.....--
Fig. 2-25 A 1-of-16 decoder.
Fig. 2-23
A
8 y c
D
Fig. 2-24
30
Digital Computer Electronics
OPR
2-16.
2-17.
2-18.
2-19.
2-20.
2-21.
2-22.
What is the boolean equation for Fig. 2-21a? The output if both inputs are high?
If all inputs are high in Fig. 2-2lb, what is the output? What is the boolean equation of the circuit? What ABC input words does the circuit recognize? What is the only word it disregards?
What is the boolean equation for Fig. 2-22a? The output if all inputs are ls? If you were to construct the truth table, how many input words would it have?
Write the boolean equation for Fig. 2-22b. If all inputs are 1s, what is the output?
If both inputs are high in Fig. 2-23, what is the output? What is the boolean e'l,uation for the circuit? Describe the truth table. /
What is the boolean equation for Fig. 2-24? How many ABCD input words are in the truth table?
Which input words does the circuit recognize?
Because of the historical connection between boolean algebra and logic, some people use the words
"true" and "false" instead of "high" and
"low" when discussing logic circuits. For instance, here's how an AND gate can be described.
If any input is false, the output is false; if all inputs are true, the output is true.
a. If both inputs are false in Fig. 2-23, what is the output?
b. What is the output in Fig. 2-23 if one input is false and the other true?
c. In Fig. 2-23 what is the output if all inputs are true? 2-23.
Figure 2-25 shows a 1-of-16 decoder. The signals coming out of the decoder are labeled LDA,
ADD, SUB, and so on. The word formed by the 4 leftmost register bits is called the OP CODE. As an equation,
OP CODE = I 15 I 14I 13 I 12
If LDA is high, what does OP CODE equal?
If ADD is high, what does it equal?
When OP CODE = 1001, which of the output signals is high?
d. Which output signal is high if OP CODE =
1111?
2-24. In Fig. 2-25, list the OP CODE words and the corresponding high output signals. (Start with
0000 and proceed in binary to 1111 . )
2-25. In the following equations the equals sign means
"is equivalent to." Classify each of the following as positive or negative logic:
a. 0 = 0 V and 1 = +5 V.
b. 0 = + 5 V and 1 = 0 V.
c. 0 = -5 V and 1 = 0 V.
d. 0 = 0 V and 1 = -5 V.
2-26. In Fig. 2-25 four output lines come from the decoder. Is it possible to add more op codes without increasing the number of output lines?
2-27. How many output lines from the decoder would be needed to have 256 op codes?
a.
b.
c.
Chapter 2
Gates
31
MORE LOGIC GATES
TABLE 3-1. TWOINPUT NOR GATE
This chapter introduces NOR and NAND gates, devices that are widely used in industry. You will also learn about De
Morgan's theorems; they help you to rearrange and simplify logic circuits.
A
B
0
0
1
0
3-1 NOR GATES
1
0
0
0
0
The NOR gate has two or more input signals but only one output signal. All inputs must be low to get a high output.
In other words, the NOR gate recognizes only the input word whose bits are all Os.
Incidentally, the boolean equation for a 2-input NOR gate is Y=A+B
(a)
Fig. 3-1
NOR
gate:
(b)
(a)
logical meaning;
(b)
standard symbol.
Read this as '' Y equals NOT A OR B.'' If you use this equation, remember that the ORing is done first, then the inversion. ;~
Two-Input Gate
Figure 3-1a shows the logical structure of a NOR gate, which is an OR gate followed by an inverter. Therefore, the final output is NOT the OR of the inputs. Originally called a NOT -OR gate, the circuit is now referred to as a
NOR gate.
Figure 3-1b is the standard symbol for a NOR gate. Notice that the inverter triangle has been deleted and the small circle or bubble moved to the OR-gate output. The bubble is a reminder of the inversion that follows the oRing.
With Fig. 3-la and b the following ideas are clear. If both inputs are low, the final output is high. If one input is low and the other high, the output is low. And if both inputs are high, the output is low.
Table 3-1 summarizes the circuit action. As you see, the
NOR gate recognizes only the input word whose bits are all
Os. In other words, all inputs must be low to get a high output. 32
(3-1)
c
y
D
(a)
Fig. 3-2
NOR
gates:
(b)
(a)
3-input;
(b)
4-input.
Three-Input Gate
Regardless of how many inputs a NOR gate has, it is still logically equivalent to an OR gate followed by an inverter.
For instance, Fig. 3-2a shows a 3-input NOR gate. The 3 inputs are ORed, and the result is inverted. Therefore, the boolean equation is
Y=A+B+C
(3-2)
The analysis of Fig. 3-2a goes like this. If all inputs are low, the result of ORing is low; therefore, the final output
A~· y TABLE 3-2. THREE-INPUT
NOR GATE
A
B
c
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
A+B+C
0
1
0
0
8
0
1
0
(a)
A
y
8
Fig. 3-3 De Morgan's first theorem: (a) with inverted inputs.
is high. If one or more inputs are high, the result of oRing is high; so the final output is low.
Table 3-2 summarizes the action of a 3-input NOR gate.
As you see, the circuit recognizes only the input word whose bits are Os. In other words, all inputs must be low to get a high output.
Four-Input Gate
Figure 3-2b is the symbol for a 4-input NOR gate. The inputs are ORed, and the result is inverted. For this reason, the boolean equation is
Y=A+B+C+D
(3-3)
The corresponding truth table has input words from 0000 to 1111. Word 0000 gives a 1 output; all other words produce a 0 output. (For practice, you should construct the truth table of the 4-input NOR gate.)
3-2 DE MORGAN'S FIRST THEOREM
Most mathematicians ignored boolean algbebra when it first appeared; some even ridiculed it. But Augustus De Morgan saw that it offered profound insights. He was the first to acclaim Boole's great achievement.
Always a warm and likable man, De Morgan himself had paved the way for boolean algebra by discovering two important theorems. This section introduces the first theorem.
The First Theorem
Figure 3-3a is a 2-input NOR gate, analyzed earlier. As you recall, the boolean equation is
Y=A+B and Table 3-3 is the truth table.
NOR
gate; (b)
AND
gate
Figure 3-3b has the inputs inverted before they reach the
AND gate. Therefore, the boolean equation is
Y = AB
If both inputs are low in Fig. 3-3b, the AND gate has high inputs; therefore, the final output is high. If one or more inputs are high, one or more AND-gate inputs must be low and the final output is low. Table 3-4 summarizes these ideas. TABLE 3-3
A
B
0
0
0
1
0
TABLE 3-4
A+B
0
0
0
A
B
AB
0
0
0
1
0
0
0
0
Compare Tables 3-3 and 3-4. They're identical. This means that the two circuits are logically equivalent; given the same inputs, the outputs are the same. In other words, the circuits of Fig. 3-3 are interchangeable.
De Morgan discovered the foregoing equivalence long before logic circuits were invented. His first theorem says
A+ B
=
AB
(3-4)
The left member of this equation represents Fig. 3-3a; the right member, Fig. 3-3b. Equation 3-4 says that Fig. 3-3a and b are equivalent (interchangeable).
Bubbled AND Gate
Figure 3-4a shows an AND gate with inverted inputs. This circuit is so widely used that the abbreviated logic symbol of Fig. 3-4b has been adopted. Notice that the inverter triangles have been deleted and the bubbles moved to the
Chapter 3
More Logic Gates
33
--~---
-----
-----~----
Here's what really counts. Equation 3-5 says that a 3-
A
input NOR gate and a 3-input bubbled AND gate are equivalent y (see Fig. 3-6a). Equation 3-6 means that a 4-input NOR gate and a 4-input bubbled AND gate are equivalent (Fig.
3-6b). Memorize these equivalent circuits; they are a visual statement of De Morgan's first theorem.
Notice in Fig. 3-6b how the input edges of the NOR gate and the bubbled AND gate have been extended. This is common drafting practice when there are many input signals.
The same idea applies to any type of gate.
8
(b)
Fig. 3-4 symbol. AND
gate with inverted inputs: (a) circuit; (b) abbreviated
EXAMPLE
3-1
Prove that Fig. 3-7a and care equivalent.
AND-gate inputs. From now on, we will refer to Fig.
3-4b as a bubbled AND gate; the bubbles are a reminder of the inversion that takes place before ANDing.
(b)
(a)
Fig. 3-5 De Morgan's first theorem.
Figure 3-5 is a graphic summary of De Morgan's first theorem. A NOR gate and a bubbled AND gate are equivalent.
As shown later, because the circuits are interchangeable, you can often reduce complicated logic circuits to simpler forms. (c)
Fig. 3-7 Equivalent De Morgan circuits.
SOLUTION
More than Two Inputs
When 3 inputs are involved, De Morgan's first theorem is written A+ B
+C
=ABC
(3-5)
For 4 inputs
A + B + C + D = ABCD
(3-6)
In both cases, the theorem says that the complement of a sum equals the product of the complements.
(a)
The final NOR gate in Fig. 3-7a is equivalent to a bubbled
AND gate. This allows us to redraw the circuit as shown in
Fig. 3-7b.
Double inversion produces noninversion; therefore, each double inversion in Fig. 3-7 b cancels out, leaving the simplified circuit of Fig. 3-7c. Figure 3-7a and c are therefore equivalent.
Remember the idea. Given a logic circuit, you can replace any NOR. gate by a bubbled AND gate. Then any double inversion (a pair of bubbles in a series path) cancels out.
Sometimes you wind up with a simpler logic circuit than you started with; sometimes not.
But the point remains. De Morgan's first theorem enables you to rearrange a logic circuit with the hope of finding a simpler equivalent circuit or perhaps getting more insight into how the original circuit works.
3-3 NAND GATES
(b)
Fig. 3-6 De Morgan's first theorem: (a) 3-input circuits; (b) 4input circuits.
34
Digital Computer Electronics
The NAND gate has two or more input signals but only one output signal. All input signals must be high to get a low output. (a)
Fig. 3-8
NAND
TABLE 3-5.
TWO-INPUT
NAND GATE
(b)
TABLE 3-6. THREEINPUT NAND GATE
gate: (a) logical meaning; (b) standard symbol.
Two-Input Gate
Figure 3-8a shows the logical structure of a NAND gate, an
AND gate followed by an inverter. Therefore, the final output is NOT the AND of the inputs. Originally called a
NOT-AND gate, the circuit is now referred to as a NAND gate. Figure 3-8b is the standard symbol for a NAND gate. The inverter triangle has been deleted and the bubble moved to the AND-gate output. If one or more inputs are low, the result of ANDing is low; therefore, the final inverted output is high. Only when all inputs are high does the ANDing produce a high signal; then the final output is low.
Table 3-5 summarizes the action of a 2-input NAND gate.
As shown, the NAND gate recognizes any input word with one or more Os. That is, one or more low inputs produce a high output. The boolean equation for a 2-input NAND gate is
Y=AB
A
B
0
0
0
1
0
A
B
c
0
0
0
0
0
0
0
1
0
I
0
1
0
AB
0
0
0
ABC
1
0
Four-Input Gate
Figure 3-9b is the symbol for a 4-input NAND gate. The inputs are ANDed, and the result is inverted. Therefore, the boolean equation is
Y
=
ABCD
(3-9)
If you construct the truth table, you will have input words from 0000 to 1111 . All words from 0000 through 1110 produce a 1 output; only the word 1111 gives a 0 output.
(3-7)
Read this as '' Y equals NOT AB. '' If you use this equation, remember that the ANDing is done first then the inversion.
3-4 DE MORGAN'S SECOND
THEOREM
The proof of De Morgan's second theorem is similar to the proof given for the first theorem. What follows is a brief explanation. (a)
Fig. 3-9
NAND
The Second Theorem
(b)
When two inputs are used, De Morgan's second theorem says that
gates: (a) 3-input; (b) 4-input.
Three-Input Gate
AB=A+B
Regardless of how many inputs a NAND gate has, it's still logically equivalent to an AND gate followed by an inverter.
For example, Fig. 3-9a shows a 3-input NAND gate. The inputs are ANDed, and the product is inverted. Therefore, the boolean equation is
Y=ABC
(3-1 0)
In words, the complement of a product equals the sum of the complements. The left member of this equation represents a NAND gate (Fig. 3-lOa); the right member stands
A
(3-8)
y
Here is the analysis of Fig. 3-9a. If one or more inputs are low, the result of ANDing is low; therefore, the final output is high. If all inputs are high, the ANDing gives a high signal; so the final output is low.
Table 3-6 is the truth table for a 3-input NAND gate. As indicated, the circuit recognizes words with one or more
Os. This means that one or more low inputs produce a high output. 8
(a)
(c)
Fig. 3-10 De Morgan's second theorem: (a) NAND gate; (b) gate with inverted inputs; (c) bubbled OR gate.
Chapter 3
More Logic Gates
OR
35
for an OR gate with inverted inputs (Fig. 3-lOb). Therefore,
De Morgan's second theorem boils down to the fact that
Fig. 3-lOa and bare equivalent.
EXAMPLE 3-2
Prove that Fig. 3-13a and c are equivalent.
Fig. 3-11 De Morgan's second theorem.
(b)
(a)
Bubbled
OR
Gate
The circuit of Fig. 3-lOb is so widely used that the abbreviated logic symbol of Fig. 3-lOc has been adopted.
From now on we will refer to Fig. 3-lOc as a bubbled OR gate; the bubbles are a reminder of the inversion that takes place before ORing.
Figure 3-11 is a visual statement of De Morgan's second theorem: a NAND gate and a bubbled.oR gate are equivalent.
This equivalence allows you to replace one circuit by the other whenever desired. This may lead to a simpler logic circuit or give you more insight into how the original circuit works. ·
More than Two Inputs
When 3 inputs are involved, De Morgan's second theorem is written
ABC=A+B+C
(3-11)
If 4 inputs are used,
ABCD = A
+B +
C
+D
(3-12)
These equations say that the complement of a product equals the sum of the complements.
(a)
(b)
Fig. 3-12 De Morgan's second theorem: (a) 3-input circuits; (b)
4-input circuits.
Figure 3-12 is a visual summary of the second theorem.
Whether 3 or 4 inputs are involved, a NAND gate and a bubbled OR gate are equivalent (interchangeable).
36
Digital Computer Electronics
(c)
Fig. 3-13 Equivalent circuits.
SOLUTION
Replace the final NAND gate in Fig. 3-13a by a bubbled OR gate. This gives Fig. 3-13b. The double inversions cancel out, leaving the simplified circuit of Fig. 3-13c. Figure
3-13a and c are therefore equivalent. Driven by the same inputs, either circuit produces the same output as the other.
So if you're loaded with NAND gates, build Fig. 3-13a. If your shelves are full of AND and OR gates, build Fig.
3-13c.
Incidentally, most people find Fig. 3-13b easier to analyze than Fig. 3-13a. For this reason, if you build Fig. 3-13a, draw the circuit like Fig. 3-13b. Anyone who sees Fig.
3-13b on a schematic diagram knows that the bubbled OR gate is the same as a NAND gate and that the built-up circuit is two NAND gates working into a NAND gate.
EXAMPLE
3-3
Figure 3-14 shows a circuit called a control matrix. At first, it looks complicated, but on closer inspection it is relatively simple because of the repetition of NAND gates. De Morgan's theorem tells us that NAND gates driving NAND gates are equivalent to AND gates driving OR gates.
The upper set of inputs T1 to T6 are called timing signals; only one of them is high at a time. T1 goes high first, then
T2 , then T3 , and so on. These signals control the rate and sequence of computer operations.
The lower set of inputs LDA, ADD, SUB, and OUT are computer instructions; only one of them is high at a time.
The outputs Cp, Ep, LM, ... , to L 0 control different registers in the computer.
Answer the following questions about the control matrix:
a.
b.
c.
Which outputs are high when T1 is high?
If T 4 and LDA are high, which outputs are high?
When T6 and SUB are high, which outputs are high?
T1
T2
T3
T4
T5
T6
I ~~--------~----~---
\7LOA--t+~-t--------~-r~------~~~~------~~~-------+--~--~------~------4---+
AOO--~~~---.-----t~-t---.-----+-t-t---.----~~~~~---4---4----f-.-----~~----~--~
SUB--+f-4-t---t--~1-~1---+---.-~t-~~--~-+--~~~~~---+~~~---.-+-+--~~--+
OUT--~~ri---f---t-t~-t---t---t-+-t-t---t---+~--~--~~~~~--+-+-+---+-~+---+-~~~
LlJ,
___.[],
)
...._,
-,
-,
-, l-,
.__,
-
.J
(
L---...-.,1
Cp
1
Ep
LM
I
Eft
Fig. 3-14 Control matrix.
SOLUTION
a.
b.
c.
Visualize T 1 high. You can quickly check out each gate and realize that Ep and LM are the only high outputs. This time T 4 and LDA are high. Check each gate and you can see that LM and E1 are the only high outputs.
When T 6 and SUB are high, the high outputs are LA,
Su, and Eu.
y
(a)
:=D--y'
(b)
Fig. 3-15 (a) gate. 3-5 EXCLUSIVE-OR GATES
An
gate recognizes words with one or more ls. The gate is different; it recognizes only words that have an odd number of 1s.
OR
EXCLUSIVE-OR
Two Inputs
Figure 3-15a shows one way to build an EXCLUSIVE-OR gate, abbreviated XOR. The upper AND gate forms the product AB, and the lower AND gate gives AB. Therefore, the boolean equation is
Y=AB+AB
(3-13)
EXCLUSIVE-OR
gate. (b) A 2-input
EXCLUSIVE-OR
Here's what the circuit does. In Fig. 3-15a two low inputs mean both AND gates have low outputs; so the final output is low. If A is low and B is high, the upper AND gate has a high output; therefore, the final output is high.
Likewise, a high A and low B result in a final output that is high. If both inputs are high, both AND gates have low outputs and the final output is low.
Table 3-7 shows the truth table for a 2-input EXCLUSIVEOR gate. The output is high when A orB is high but not both; this is why the circuit is known as an EXCLUSIVE-OR gate. In other words, the output is a I only when the inputs are different.
Chapter 3
More Logic Gates
37
_ _ _ _ __ _ j_ _
-----~ - - - - - - - ---
--------
--------
r-
TABLE 3-7. TWO-
A
INPUT
8
A
B
0
0
0
1
XOR
GATE
AB
+
c
AB
J y 0
0
0
(a)
1
0
0 y Logic Symbol and Boolean Sign
(b)
Figure 3-15b is the standard symbol for a 2-input XOR gate.
Whenever you see this symbol, remember the action: the inputs must be different to get a high output.
A word equation for Fig. 3-15b is
Y =A XOR B
(3-14)
In boolean algebra the sign (f) stands for XOR addition.
This means that Eq. 3-14 can be written
Y=A(f)B
(3-15)
Fig. 3-16 A 4-input EXCLUSIVE-OR gate: (a) circuit with 2-input xoR gates; (b) logic symbol.
It's possible to substitute input values into the equation and solve for the output. For instance, if A through C are low and D is high, y = (0 (f) 0) (f) (0 (f) 1)
=08:)1
= 1
Read this as '' Y equals A XOR B.''
Given the inputs, you can substitute and solve for the output. For instance, if both inputs are low,
Y=O(f)O=O because 0 XORed with 0 gives 0. If one input is low and the other high,
Y=O(f)1=1
because 0 XORed with l produces 1. And so on.
Here's a summary of the four possible XOR additions:
08:)0
08:)1
18:)0
18:)1
0
0
Remember these four results; we will be using XOR addition when we get to arithmetic circuits.
Four Inputs
In Fig. 3-16a the upper gate produces A (f) B, while the lower gate gives C (f) D. The final gate XORs both of these sums to get
Y = (A (f) B) (f) (C (f) D)
38
Digital Computer Electronics
(3-16)
One way to get the truth table is to plow through all the input possibilities.
Alternatively, you can analyze Fig. 3-16a as follows. If all inputs are Os, the first two gates have 0 outputs; so the final gate has a 0 output. If A to C are Os and D is a 1, the upper gate has a 0 output, the lower gate has a 1 output, and the final gate has a 1 output. In this way, you can analyze the circuit action for all input words.
Table 3-8 summarizes the action. Here is an important property: each input word with an odd number of 1s produces a 1 output. For instance, the first input word to produce a 1 output is 000 I; this word has an odd number of 1s. Tl}e next word with a I output is 0010; again an odd number of 1s. A I output also occurs for these words:
0100, 0111, 1000, 10II, 1101, and 1110, all of which have an odd number of 1s.
The circuit of Fig. 3-16a recognizes words with an odd number of Is; it disregards words with an even number of
1s. Figure 3-16a is a 4-input XOR gate. In this book, we will use the abbreviated symbol of Fig. 3-16b to represent a 4-input XOR gate. When you see this symbol, remember the action: the circuit recognizes words with an odd number of Is.
Any Number of Inputs
Using 2-input XOR gates as building blocks, we can make
XOR gates with any number of inputs. For example, Fig.
TABLE 3-8. FOUR-INPUT
GATE
The first word has even parity because it contains ten 1s; the second word has odd parity because it contains eleven
1s.
XOR gates are ideal for testing the parity of a word. XOR gates recognize words with an odd number of 1s. Therefore, even-parity words produce a low output and odd-parity words produce a high output.
XOR
Comment
A
B
c
D
y
Even
Odd
Odd
Even
Odd
Even
Even
Odd
Odd
Even
Even
Odd
Even
Odd
Odd
Even
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
1
1
1
1
1
1
1
....__~-----·=-<· .<.
(a)
Fig. 3-17
XOR
oEXAMPLE
0
..,t,,
3-4
What is the output of Fig. 3-18 for each of these input words? a. 1010 1100 1000 UOO
b. 1010 1100 1000 1101
1
b
0
1
0
1
1
0
16 bits
ODD
(b)
gates: (a) 3-input; (b) 6-input.
Fig. 3-18 Odd-parity tester.
3-17a shows the abbreviated symbol for a 3-input XOR gate, and Fig. 3-17b is the symbol for a 6-input xoR gate. The final output of any xoR gate is the XOR sum of the inputs:
Y=A(jjB(jjC···
SOLUTION
a.
The word has seven 1s, an odd number. Therefore, the output signal is
(3-17)
ODD
What you have to remember for practical work is this: an XOR gate, no matter how many inputs, recognizes only words with an odd number of Is.
b.
=1
The word has eight 1s, an even number. Now
ODD= 0
Parity
Even parity means a word has an even number of Is. For instance, 110011 has even parity because it contains four
1s. Odd parity means a word has an odd number of 1s. As an example, 110001 has odd parity because it contains three 1s.
Here are two more examples:
1111000011110011
1111 0000 1111 011 1
(Even parity)
(Odd parity)
This is an example of an odd-parity tester. An evenparity word produces a low output. An odd-parity word results in a high output.
EXAMPLE
3-5
The 7-bit register of Fig. 3-19 stores the letter A in ASCII form. What does the 8-bit output word equal?
Chapter 3
More Logic Gates
39
--
- - ----'-------
Because of the 1-bit error, we receive letter C when letter
A was actually sent.
7-bit register
A6
A4
A5
A3
A2
A,
Ao
One solution is to transmit an odd-parity bit along with the data word and have an XOR gate test each received word for odd parity. For instance, with a circuit like Fig.
3-19 the letter A would be transmitted as
1100 0001
An XOR gate will test this word when it is received. If no error has occurred, the XOR gate will recognize the word.
On the other hand, if a 1-bit error has crept in, the XOR gate will disregard the received word and the data can be rejected. A final point. When errors come, they are usually 1-bit errors. This is why the method described catches most of the errors in transmitted data.
11
t
Odd-parity bit Instruction or data bits
8-bit word with odd parity
EXAMPLE
3-6
What does the circuit of Fig. 3-20 do?
Fig. 3-19 Odd-parity generator.
A
INVERT
SOLUTION
The ASCII code for letter A is
100 0001 y (see Table 1-6 for the ASCII code). This word has an even parity, which means that the XOR gate has a 0 output.
Because of the inverter, the overall output of the circuit is the 8-bit word
1100 0001
(A)
Somewhere along the line, one of the bits may be changed.
If the X1 bit changes, the received data will be
100 0011
40
SOLUTION
When INVERT
Notice that this has odd parity.
The circuit is called an odd-parity generator because it produces an 8-bit output word with odd parity. If the register word has even parity, 0 comes out of the XOR gate and the odd-parity bit is 1. On the other hand, if the register word has odd parity, a 1 comes out of the XOR gate and the oddparity bit is 0. No matter what the register contents, the odd-parity bit and the register bits form a new 8-bit word that has odd parity.
What is the practical application? Because of transients, noise, and other disturbances, 1-bit errors sometimes occur in transmitted data. For instance, the letter A may be transmitted over phone lines in ASCII form:
100 0001
Fig. 3-20
(C)
Digital Computer Electronics
=
0 and A
=
0,
Y=O(f)O=O
When IN.VERT
=
0 and A
=
1,
Y=O(f)1=1
In either case, the output is the same as A; that is,
Y=A for a low INVERT signal.
On the other hand, when INVERT
=
Y=1(f)O=
When INVERT = 1 and A = 1,
Y=1(f)1=0
1 and A
0,
This time, the output is the complement of A. As an equation, register contents. As demonstrated in Example 3-6, each
XOR gate acts like this. A low INVERT results in
Y=A for a high INVERT signal.
To summarize, the circuit of Fig. 3-20 does either of two things. It transmits A when INVERT is 0 and A when
INVERT is 1.
3-6 THE CONTROLLED INVERTER
and a high INVERT gives
So each bit is either transmitted or inverted before reaching the final output.
Visualize the register contents as a word A7A6 · • • A0 and the final output as a word Y7Y6 • • • Y0 . Then a low
INVERT means
The preceding example suggests the idea of a controlled inverter, a circuit that transmits a binary word or its I' s complement. On the other hand, a high INVERT results in
The 1 's Complement
Complement each bit in a word and the new word you get is the 1's complement. For instance, given
As a concrete example, suppose the register word is
1100 0111 the 1's complement is
Then, a low INVERT gives an output word of
0011 1000
Each bit in the original word is inverted to get the 1's complement. The Circuit
The XOR gates of Fig. 3-21 form a controlled inverter
(sometimes called a programmed inverter). This circuit can transmit the register contents or the 1's complement of the
and a high INVERT produces
The controlled inverter of Fig. 3-21 is important. Later you will see how it is used in solving arithmetic and logic problems. For now, all you need to remember is the key idea. The output word from a controlled inverter equals the
8-bit register
Fig. 3-21 Controlled inverter.
Chapter 3
More Logic Gates
41
TABLE 3-9.
TWO-INPUT
XNOR GATE
input word when INVERT is low; the output word equals the 1's complement when INVERT is high.
Boldface Notation
After you understand an idea, it simplifies discussions and equations if you use a symbol, letter, or other sign to represent the idea. From now on, boldface letters will stand for binary words.
For instance, instead of writing
we can write
A
A
B
y
0
0
0
1
0
0
0
Because of the inversion on the output side, the truth table of an XNOR gate is the complement of an XOR truth table. As shown in Table 3-9, the output is high when the inputs are the same. For this reason, the 2-input XNOR gate is ideally suited for bit comparison, recognizing when two input bits are identical. (Example 3-7 tells you more about bit comparison.)
11100110
Likewise, instead of
0001 1001 the simpler equation
y
0001 1001
can be used.
This is another example of chunking. We are replacing long strings like A7A6 • • • A0 and Y7 Y6 • • • Y0 by A and
Y. This chunked notation will be convenient when we get to computer analysis.
This is how to summarize the action of a controlled inverter: y
=
{!
when INVERT when INVERT
=
=
0
1
(Note: A boldface letter with an overbar means that each bit in the word is complemented; if A is a word, A is its l 's complement.)
(a)
Fig. 3-23
XNOR
(b)
gates: (a) 3-input; (b) 4-input.
Figure 3-23a is the symbol for a 3-input XNOR gate, and
Fig. 3-23b is the 4-input XNOR gate. Because of the inversion on the output side, these XNOR gates perform the complementary function of XOR gates. Instead of recognizing oddparity words, XNOR gates recognize even-parity words.
EXAMPLE 3-7
What
do~s
the circuit of Fig. 3-24 do?
3-7 EXCLUSIVE-NOR GATES
SOLUTION
The EXCLUSIVE-NOR gate, abbreviated XNOR, is logically equivalent to an xoR gate followed by an inverter. For example, Fig. 3-22a shows a 2-input XNOR gate. Figure
3-22b is an abbreviated way to draw the same circuit.
:=Dr-y
(a)
(b)
Fig. 3-22 A 2-input XNOR gate: (a) circuit; (b) abbreviated symbol.
42
Digital Computer Electronics
The circuit is a word comparator; it recognizes two identical words. Here is how it works. The leftmost XNOR gate compares A 5 and B 5 ; if they are the same, Y 5 is a l. The second XNOR gate compares A4 and B 4 ; if they are the same,
Y4 is a l. In tum, the remaining XNOR gates compare the bits that are left, producing a l output for equal bits and a
0 output for unequal bits.
If the words A and B are identical, all XNOR gates have high outputs and the AND gate has a high EQUAL. If words
A and B differ in one or more bit positions, the AND gate has a low EQUAL.
B register
A register
'>
EQUAL
Fig. 3-24 Word comparator.
GLOSSARY controlled inverter This circuit produces the 1's complement of the input word. One application is binary subtraction. It is sometimes called a programmed inverter.
De Morgan's theorems The first theorem says that a NOR gate is equivalent to a bubbled AND gate. The second theorem says that a NAND gate is equivalent to a bubbled
OR gate. even parity An even number of Is in a binary word.
NAND gate Equivalent to an AND gate followed by an inverter. All inputs must be high to get a low output.
NOR gate Equivalent to an OR gate followed by an inverter.
All inputs must be low to get a high output.
odd parity An odd number of Is in a binary word. parity generator A circuit that produces either an odd- or even-parity bit to go along with the data.
XNOR gate Equivalent to an EXCLUSIVE-OR gate followed by an inverter. The output is high only when the input word has even parity.
XOR gate An EXCLUSIVE-OR gate. It has a high output only when the input word has odd parity. For a 2-input
XOR gate, the output is high only when the inputs are different. SELF-TESTING REVIEW to get a low output. De Morgan's second theorem says that a NAND gate is equivalent to a bubbled
_____ gate.
Read each of the following and provide the missing words.
Answers appear at the beginning of the next question.
1.
2.
3.
A NOR gate has two or more input signals. All inputs must be to get a high output. A NOR gate recognizes only the input word whose bits are
- - - - - · The NOR gate is logically equivalent to an OR gate followed by an _ _ __
(low, Os, inverter) De Morgan's first theorem says that a NOR gate is equivalent to a bubbled _ _ __ gate. (AND) A NAND gate is equivalent to an AND gate followed by an inverter. All inputs must be _ _ __
4.
5.
(high, OR) An XOR gate recognizes only words with an number of ls. The 2-input XOR gate has a high output only when the input bits are
- - - - - · XOR gates are ideal for testing parity because even-parity words produce a _ _ _ __ output and odd-parity words produce a _ _ _ __ output. (odd, different, low, high) An odd-parity generator produces an odd-parity bit to go along with the data.
Chapter 3
More Logic Gates
43
6.
The parity of the transmitted data is
. An
XOR gate can test each received word for parity, rejecting words with parity. (odd, even) A controlled inverter is a logic circuit that transmits a binary word or its complement. 7.
(1 's) The EXCLUSIVE-NOR gate is equivalent to an
XOR gate followed by an inverter. Because of this, even-parity words produce a high output.
·'
PROBLEMS
3-1.
In Fig. 3-25a the two inputs are connected together. If A is low, what is Y? If A is high, what is Y? Does the circuit act like a noninverter or an inverter? 3-5.
The outputs in Fig. 3-27 are cross-coupled back to the inputs of the_NOR gates. If R = 0 and S =
1, what do Q and Q equal?
A---Q>--Y
(a)
A
y
8
(b)
Fig. 3-27 Cross-coupled NOR gates.
Fig. 3·25
3-6.
3-2.
3-3.
3-4.
What is the output in Fig. 3-25b if both inputs are low? If one is low and the other high? If both are high? Does the circuit act like an OR gate or an
AND gate?
Figure 3-26 shows a NOR-gate crossbar switch. If all X and Y inputs are high, which of the Z outputs is high? If all inputs are high except X 1 and Y 2 , which Z output is high? If X 2 and Y 0 are low and all other inputs are high, which Z output is high?
In Fig. 3-26, you want Z7 to be l and all other Z outputs to be 0. What values must the X and Y inputs have?
I
Y',
Fig. 3-26 NOR-gate crossbar switch.
44
Digital Computer Electronics
3-7.
3-8.
3-9.
3-10.
3-11.
3-12.
If R = __! and S = 0 in Fig. 3-27, what does Q equal? Q?
Prove that Fig. 3-28a and bare equivalent.
What is the output in Fig. 3-28a if all inputs are
Os. If all inputs are ls?
What is the output in Fig. 3-28b if all inputs are
Os. If all inputs are ls?
A NOR has 6 inputs. How many input words are in its truth table? What is the only input word that produces a 1 output?
In Fig. 3-28a how many input words are there in the truth table?
What is the output in Fig. 3-29 if all inputs are low? If all inputs are high?
(a)
(b)
/
<:_;
Fig. 3-28
b.
A
c.
y
c
d.
0
3-18.
Fig. 3-29
3-13.
3-14.
3-15.
If all inputs are low except X 2 and Y1, which
Z output is low?
8
How many words are in the truth table of Fig.
3-29. What is the value of Y for each of the following? a. ABCD = 0011
b. ABCD = 0110
c. ABCD = 1001
d. ABCD = llOO
Which ABCD input words does the circuits of
Fig. 3-29 recognize?
In Fig. 3-30a the two inputs are connected together. If A = 0 what does Y equal? If A = I , what does Y equal? Does the circuit act like a noninverter or an inverter?
If all inputs are low except X0 and Y2 , which
Z output is low?
To get a low Z 8 output, which inputs must be
high?
In Fig. 3-31, what are the outputs if R
S = I?
=
0 and
s---'-1
Fig. 3-31 Cross-coupled
3-19.
3-20.
3-21.
NAND
gates.
If R = __! and S = 0 in Fig. 3-31, what does Q equal? Q?
What is the output in Fig. 3-32a if all inputs are
Os? If all inputs are ls?
How many input words are there in the truth table of Fig. 3-32a?
WJ
)_
::
(a)
/-,
A
8
(b)
Fig. 3-30
3-16.
.--3-17.
What is the output in Fig. 3-30b if both inputs are low? If one input is low and the other high? If both are high? Does the circuit act like an OR gate or an AND gate?
Suppose the NOR gates of Fig. 3-26 are replaced by NAND gates. Then you've got a NAND-gate crossbar switch.
a. If all X and Y inputs are low, which Z output is low?
Fig. 3-32
Chapter 3
More Logic Gates
45
\
3-22.
Prove that Fig. 3-32a and b are equivalent.
3·23. What is the output in Fig. 3-33 if all inputs are
3-24.
3-25.
low? If they are all high?
How many words are in the truth table of Fig.
3-33? What does Y equal for each of the following:
a. ABCDE = OOlll
b. ABCDE = 10110
c. ABCDE = 11010
d. ABCDE = 101ol
In Fig. 3-34 the inputs are T4 , JMP, JAM, JAZ,
AM, and Az; the output is Lp. What is the output for each of these input conditions?
a. All inputs are Os.
b. All inputs are low except T4 and JMP.
3-26.
c.
All inputs are low except T 4 , JAZ, and Az.
d.
The only high inputs are T4 , JAM, and AM.
Figure 3-35 shows the control matrix discussed in
Example 3-3. Only one of the timing signals T 1 to
T6 is high at a time. Also, only one of the instructions, LDA to OUT, is high at a time. Which are the high outputs for each of the following conditions?
g. T 5 and ADD high
a. T 1 high
b. T 2 high
h. T6 and ADD high
c. T 3 high
i. T4 and SUB high
j. T 5 and SUB high
d. T4 and LDA high
k. T6 and SUB high
e. T 5 and LDA high
1. T4 and OUT high
f. T4 and ADD high
JMP
JAM
JAZ
y
Fig. 3-33
Fig. 3-34
I
I
~
LOA
ADD
SUB
OUT
Q_On
~e~-
~~
"---Jl,.
I
Cp
I
Ep
y
LM
I
ER
Fig. 3-35 Control matrix.
46
Digital Computer Electronics
~0
~~
I
'--
~- LJ= ~) c
p.~
I
19 L)= ~)
MI
3-27.
Figure 3-36 shows a binary-to-Gray-code converter. (Gray code is a special code used in analog-to-digital conversions.) The input word is
X4 X3 • • • X0 , and the output word is Y4 Y3 • • •
Y0 • What does the output word equal for each of these inputs?
a. X4X3 • • • X0 = 10011
b. X4X 3 • • • Xo = 01110
c. X4X3 • • • Xo = 10101
d. X4 X3 • • • Xo = 11100
i
}<)
x3
1
A
CARRY
SUM
Fig. 3-37
3-32.
3-33.
y4
y3·
y2
y1
3-34.
Fig. 3-36 Binary-tcr-Gray-code converter.
3-28.
3-29.
3-30.
3-31.
How many input words are there in the truth table of an 8-input xoR gate?
How can you modify Fig. 3-19 so that it produces an 8-bit output word with even parity?
In the controlled inverter of Fig. 3-21, what is the output word Y for each of these conditions?
a. A = 1100 1111 and INVERT = 0
b. A = 0101 0001 and INVERT = 1
c. A = 1110 1000 and INVERT = 1
d. A = 1010 0101 and INVERT = 0
The inputs A and B of Fig. 3-37 produce outputs of CARRY and SUM. What are the values of
CARRY and SUM for each of these inputs?
a. A = 0 and B = 0
b. A = 0 and B = 1
c. A
1 and B = 0
d. A = 1 and B = 1
8
I
3-35.
In Fig. 3-37, what is the boolean equation for
CARRY? For SUM?
What is the 1's complement for each of these numbers? a. llOO 0011
b. 1010 1111 0011
c. 1110 0001 1010 0011
d. 0000 1111 0010 1101
What is the output of a 16-input XNOR gate for each of these input words?
a. 0000 0000 0000 1111
b. 1111 0101 1l10 llOO
c. 0101 1100 0001 0011
d. 111100001010 0110
The boolean equation for a certain logic circuit is
Y = AB + CD + AC. What does Y equal for each of the following:
a. ABCD = 0000
b. ABCD = 0101
c. ABCD = 1010
d. ABCD = 1001
'
'
0
Chapter 3
More Logic Gates
47
TTL CIRCUITS
In 1964 Texas Instruments introduced transistor-transistor logic (TTL), a widely used family of digital devices. TTL is fast, inexpensive, and easy to use. This chapter concentrates on TTL because once you are familiar with it, you can branch out to other logic families and technologies.
means that you can connect the output of one device to the input of another). Compatibility permits a large number of different combinations.
Bipolar Families
In the bipolar category are these basic families:
4-1 DIGITAL INTEGRATED
CIRCUITS
Using advanced photographic techniques, a manufacturer can produce miniature circuits on the surface of a chip (a small piece of semiconductor material). The finished network is so small you need a microscope to see the connections. Such a circuit is called an integrated circuit
(IC) because the components (transistors, diodes, resistors) are an integral part of the chip. This is different from a discrete circuit, in which the components are individually connected during assembly.
DTL
TTL
ECL
Diode-transistor logic
Transistor-transistor logic
Emitter-coupled logic
DTL uses diodes and transistors; this design, once popular, is now obsolete. TTL uses transistors almost exclusively; it has become the most popular family of SSI and MSI chips. ECL, the fastest logic family, is used in high-speed applications. MOS Families
In the MOS category are these families:
Levels of Integration
Small-scale integration (SSI) refers to ICs with fewer than
12 gates on the same chip. Medium-scale integration (MSI) means from 12 to 100 gates per chip. And large-scale integration (LSI) refers to more than 100 gates per chip.
The typical microcomputer has its microprocessor, memory, and 1/0 circuits on LSI chips; a number of SSI and MSI chips are used to support the LSI chips.
Technologies and Families
The two basic technologies for manufacturing digital ICs are bipolar and MOS. The first fabricates bipolar transistors on a chip; the second, MOSFETS. Bipolar technology is preferred for SSI and MSI because it is faster. MOS technology dominates the LSI field because more MOSFETs can be packed on the same chip area.
A digital family is a group of compatible devices with the same logic levels and supply voltages ("compatible"
48
PMOS
NMOS
CMOS
p-Channel MOSFETs n-Channel MOSFETs
Complementary MOSFETs
PMOS, the oldest and slowest type, is becoming obsolete.
NMOS dominates the LSI field, being used for microprocessors and memories. CMOS, a push-pull arrangement of n- and p-channel MOSFETs, is extensively used where low power consumption is needed, as in pocket calculators, digital wristwatches, etc.
4-2 7400 DEVICES
The 7400 series, a line of TTL circuits introduced by Texas
Instruments in 1964, has become the most widely used of all bipolar ICs. This TTL family contains a variety of SSI and MSI chips that allow you to build all kinds of digital circuits and systems.
r-------.-------~--~+5V
diode of Q3 reverse-biased. In this way, only Q4 conducts when the output is low.
Totem-Pole Output
Why are totem-pole transistors used? Because they produce a low output impedance. Either Q 3 acts like an emitter follower (high output) or Q4 is saturated (low output).
Either way, the output impedance is very low. This is important because it reduces the switching time. In other words, when the output changes from low to high, or vice versa, the low output impedance implies a short RC time constant; this short time constant means that the output voltage can change quickly from one state to the other.
A
8
Fig. 4-1 Standard TTL
NAND
gate.
Propagation Delay Time and Power Dissipation
Standard TTL
Figure 4-1 shows a TTL NAND gate. The multiple-emitter input transistor is typical of all the gates and circuits in the
7400 series. Each emitter acts like a diode; therefore, Q 1 and the 4-k!l resistor act like a 2-input AND gate. The rest of the circuit inverts the signal; therefore, the overall circuit acts like a 2-input NAND gate.
The output transistors (Q 3 and Q4 ) form a totem-pole connection, typical of most TTL devices. Either one or the other is on. When Q3 is on, the output is high; when Q4 is on, the output is low. The advantage of a totem-pole connection is its low output impedance.
Ideally, the input voltages A and B are either low
(grounded) or high (5 V). If A or B is low, Q 1 saturates.
This reduces the base voltage of Q2 to almost zero.
Therefore, Q2 cuts off, forcing Q4 to cut off. Under these conditions, Q3 acts like an emitter follower and couples a high voltage to the output.
On the other hand, when both A and B are high, the collector diode of Q 1 goes into forward conduction; this forces Q2 and Q4 into saturation, producing a low output.
Table 4-l summarizes all input and output conditions.
Incidentally, without diode D 1 in the circuit, Q3 would conduct slightly when the output is low. To prevent this, the diode is inserted; its voltage drop keeps the base-emitter
TABLE 4-1.
TWOINPUT
NAND GATE
A
B
0
0
0
y
1
0
0
Two quantities needed for our later discussions are power dissipation and propagation delay time. A standard TTL gate has_ a power dissipation ?f about ~mW. It may vary from this value because of signal levels, tolerances, etc., but on the average, it's 10 mW per gate.
The propagation delay time is the amount of time it takes for the output of a gate to change after the inputs have changed. The propagation delay time of a TTL gate is in the vicinity of 10 ns.
Device Numbers
By varying the design of Fig. 4-1 manufacturers can alter the number of inputs and the logic function. The multipleemitter inputs and the totem-pole outputs are still used, no matter what the design. (The only exception is an open collector, discussed later.)
Table 4-2 lists some of the 7400-series TTL gates. For instance, the 7400 is a chip with four 2-input NAND gates in one package. Similarly, the 7402 has four 2-input NOR gates, the 7404 has six inverters, and so on.
TABLE 4-2. STANDARD TTL
Device number
Description
7400
7402
7404
7408
7410
7411
7420
7421
7427
7430
7486
Quad 2-input NAND gates
Quad 2-input NOR gates
Hex inverter
Quad 2-input AND gates
Triple 3-input NAND gates
Triple 3-input AND gates
Dual 4-input NAND gates
Dual 4-input AND gates
Triple 3-input NOR gates
8-input NAND gate
Quad 2-input XOR gates
Chapter4
TTL Circuits
49
5400 Series
Any device in the 7400 series works over a temperature range of oo to 70°C and over a supply range of 4.75 to
5.25 V. This is adequate for commercial applications. The
5400 series, developed for the military applications, has the same logic functions as the 7400 series, except that it works over a temperature range of -55 to l25°C and over a supply range of 4.5 to 5.5 V. Although 5400-series devices can replace 7400-series devices, they are rarely used commercially because of their much higher cost.
High-Speed TTL
The cir~uit of Fig. 4-1 is called standard TTL. By decreasing the resistances a manufacturer can lower the internal time constants; this decreases the propagation delay time. The s_maller resistances, however, increase the power dissipation. This variation is known as high-speed TTL. Devices of this type are numbered 74HOO, 74H01, 74H02, and so on. A high-speed TTL gate has a power dissipation around
22 mW and a propagation delay time of approximately 6 ns. This virtually el_i~~~~?atl,lnttion delay.time, which means better switching speed. This variation is called Schottky
TTL; the devices are numbered 74SOO, 74S01, 74S02, and so forth.
Schottky TTL devices are very fast, capable of operating reliably at 100 MHz. The 74SOO has a power dissipation around 20 mW per gate and a propagation delay time of approximately 3 ns.
Low-Power Schottky TTL
By increasing internal resistances as well as using Schottky diodes manufacturers have come up with the best compromise between low power and high speed: low-power Schottky
TTL. Devices of this type are numbered 74LSOO, 74LS01,
74LS02, etc. A low-power Schottky gate has a power dissipation of around 2 mW and a propagation delay time of approximately 10 ns, as shown in Table 4-3.
Standard TTL and low-power Schottky TTL are the mainstays of the digital designer. In other words, of the five TTL types listed in Table 4-3, standard TTL and lowpower Schottky TTL have emerged as the favorites of the digital designers. You will see them used more than any other bipolar types.
Low-Power TTL
By increasing the internal resistances a manufacturer can reduce the power dissipation of TTL gates. Devices of this type are called low-power TTL and are numbered 74LOO
74L01, 74L02, etc. These devices are slower than standard
TTL because of the larger internal time constants. A lowpower TTL gate has a power dissipation of approximately
1 mW and a propagation delay time around 35 ns.
Schottky TTL
With standard TTL, high-speed TTL, and low-power TTL, the transistors go into saturation causing extra carriers to flood the base. If you try to switch this transistor from saturation to cutoff, you have to wait for the extra carriers to flow out of the base; the delay is known as the saturation delay time.
One way to reduce saturation delay time is with Schottky
TTL. The idea is to fabricate a Schottky diode along with each bipolar transistor of a TTL circuit, as shown in Fig.
4-2. Because the Schottky diode has a forward voltage of only 0.4 V, it prevents the transistor from saturating fully.
Fig. 4-2 Schottky diode prevents transistor saturation.
50
Digital Computer Electronics
4-3 TTL CHARACTERISTICS
7400-series devices are guaranteed to work reliably over a temperature range of 0 to 70°C and over a supply range of
4.75 to 5.25 V. In the discussion that follows, worst case means that the parameters (characteristics like maximum input current, minimum output voltage, and so on) are measured under the worst conditions of temperature and voltage-maximum temperature and minimum voltage for some parameters, minimum temperature and maximum voltage for others, or whatever combination produces the worst values.
Floating Inputs
When a TTL input is low or grounded, a current h
(conventional direction) exists in the emitter, as shown in
TABLE 4-3. TTL POWER-DELAY VALUES
Type
Power, mW Delay time, ns Low-power
Low-power Schottky
Standard
High-speed
Schottky
1
2
10
22
20
35
10
10
6
3
+5V--+---
+5V=e--+5
4kQ
v
+5V=e--4kQ
Open~
(high)~
low
Take the other extreme. Suppose V1 is 5 V in Fig. 4-4.
This is a high input; therefore, the output of the inverter is low. V1 can decrease all the way down to 2 V, and the output will still be low. Data sheets list this worst -case high input as
VIH = 2
Open
v
VEL = 0.8
---
(b)
(a)
VE to 0.8 V and still have a high output. The maximum low-level input voltage is designated VEL· Data sheets list this worst-case low input as
v
---
f
(c)
(d)
1(
In other words, any input voltage from 2 to 5 V is a high input for TTL devices.
Fig. 4-3 Open or floating input is the same as a high input.
Worst-Case Output Voltages
Fig. 4-3a. On the other hand, when a TTL input is high
(Fig. 4-3b), the emitter diode cuts off and the emitter current is approximately zero.
When a TTL input is floating (unconnected), as shown in Fig. 4-3c, no emitter current is possible. Therefore, a floating TTL input is equivalent to a high input. In other words, Fig. 4-3c produces the same output as Fig. 4-3b.
This is important to remember. In building circuits any floating TTL input will act like a high input.
Figure 4-3d emphasizes the point. The input is floating and is equivalent to a high input; therefore, the output of the inverter is low.
Ideally, 0 V is the low output, and 5 V is the high output.
We cannot attain these ideal values because of internal voltage drops. When the output is low in Fig. 4-4, Q4 is saturated and has a small voltage drop across it. With TTL devices, any voltage from 0 to 0.4 V is a low output.
When the output is high, Q3 acts like an emitter follower.
Because of the drop across Q3 , D 1 , and the 130-fl resistor, the output is less than 5 V. With TTL devices, a high output is between 2.4 and 3.9 V, depending on the supply voltage, temperature, and load.
This means that the worst-case output values are
VoL= 0.4 V
r-----.----.---o+5V
4kQ
1.6 kQ
130 [2
VoH = 2.4 V
Table 4-4 summarizes the worst-case values. Remember that they are valid over the temperature range (0 to 70°C) and supply range (4.75 to 5.25 V).
Compatibility
The values shown in Table 4-4 indicate that TTL devices are compatible. This means that the output of a TTL device can drive the input of another TTL device, as shown in
Fig. 4-5a. To be specific, Fig. 4-5b shows a low TTL output (0 to 0.4 V). This is low enough to drive the second
TTL device because any input less than 0.8 V is a low input. Fig. 4-4 TTL inverter.
TABLE 4-4. TTL STATES (WORST
CASE)
Worst-Case Input Voltages
Figure 4-4 shows a TTL inverter with an input voltage of
VE and an output voltage of V0 • When VE is 0 V (grounded), the output voltage is high. With TTL devices, we can raise
Low
High
Output, V
Input, V
0.4
2.4
0.8
Chapter 4
-
-~------------
2
TTL Circuits
51
------·-----------
direction shown. The charges flow from the emitter of Q 1
TTL
TTL device device
Va
"'
(a)
------4..._- +5
v
130Q
to the collector of Q4 • Because it is saturated, Q4 acts like a current sink; charges flow through it to ground like water flowing down a drain.
On the other hand, when a standard TTL output is high
(Fig. 4-5c), a reverse emitter current of 40 J.LA (worst case) exists in the direction shown. Charges flow from Q 3 to the emitter of Q 1 • In this case, Q 3 is acting like a source.
Data sheets lists the worst-case input currents as
+5V--+---
IIL = -1.6 rnA
IIH
= 40 J.LA
The minus sign indicates that the current is out of the device; plus means the current is into the device. All data sheets use this convention.
0 to 0.4 V
Less than 0.8 V is low input
Standard Loading
A TTL device can source current (high output) or it can sink current (low output). Data sheets of standard TTL devices indicate that any 7400-series device can sink up to
16 rnA, designated as
(b)
---+--+5V
130Q
IoL = 16 rnA
+5V--+--
and can source up to 400 J.LA, designated loH =
-400 J.LA
2.4 to 3.9 V
More than 2 V is high input
(c)
Fig. 4-5 Sourcing and sinking current.
Similarly, Fig. 4-5c shows a high TTL output (2.4 to
3.9 V). This is more than enough to drive the second TTL because any input greater than 2 V is a high input.
Noise Margin
In the worst case, there is a margin ofO..Jl-\'. between the driver and the load in Fig. 4-5b and c. This difference, called the noise margin, represents protection against noise.
In other words, the connecting wire between a TTL driver and a TTL load may pick up stray noise voltages. As long as these induced voltages are less than 0.4 V, we get no false triggering of the TTL load.
Sourcing and Sinking
When a standard TTL output is low (Fig. 4-5b), an emitter current of approximately 1.6 rnA (worst case) exists in the
52
Digital Computer Electronics
(Again, a minus sign means that the current is out of the device and a plus sign means that it's into the device.)
A single TTL load has a low-level input current of 1.6 rnA (Fig., 4-5b) and a high-level input current of 40 J.LA
(Fig. 4-5c). Since the maximum output currents are 10 times as large, we can connect up to 10 TTL emitters to any TTL output.
Figure 4-6a illustrates a low output. Here you see the
TTL driver sinking 16 rnA, the sum of 10 TTL load currents. In this state, the output voltage is guaranteed to be 0.4 V or less. If you try connecting more than 10 emitters, the output voltage may rise above 0.4 V.
Figure 4-6b shows a high output with the driver sourcing
400 J.LA for 10 TTL loads of 40 J.LA each. For this maximum loading, the output voltage is guaranteed to be 2.4 V or more under worst-case conditions.
Loading Rules
The maximum nnmber of TTL emitters that can be reliably driven under worst-case conditions is called the fanout.
With standard TTL, the fanout is 10, as shown in Fig.
4-6. Sometimes, we may want to use a standard TTL device to drive low-power Schottky devices. In this case, the fanout increases because low-power Schottky devices have less input current.
1.6mA
the right. Pick the driver, pick the load, and read the fanout at the intersection of the two. For instance, the fanout of a standard device (74) driving low-power Schottky devices
(74LS) is 20. As -another example, the fanout of a lowpower device (74L) driving high-speed devices (74H) is only 1.
TTL device 1
1.6mA
16mA
TTL
TTL
device
2
device
I
i
4-4 TTL OVERVIEW
I
I
I
1.6mA
Let's take a look at the logic functions available in the
7400 series. This overview will give you an idea of the variety of gates and circuits found in the TTL family. As guide, Appendix 3 lists some of the 7400-series devices.
You will find it useful when looking for a device number or logic function.
TTL device 10
(a)
40
J.LA
TTL device 1
400 pA
40pA
TTL
TTL
device
2
device
I
(a}
(b)
I
I
I
I
I
40pA
TTL device 10
,,
(b)
Fig. 4-6 Fanout of standard TTL devices: (a) low output; (b) high output.
(c)
By examining data sheets for the different TTL types we can calculate the fanout for all possible combinations. Table
4-5 summarizes these fan outs, which may be useful if you ever have to mix TTL types.
Read Table 4-5 as follows. The series numbers have been abbreviated; 74 stands for 7400 series, 74H for 74HOO series, and so forth. Drivers are on the left and loads on
TABLE 4-5. FANOUTS
Fig. 4-7 Three, four, and eight inputs.
NAND Gates
To begin with, the NAND gate is the backbone of the entire series. All devices in the 7400 series are derived from the
2-input NAND gate shown in Fig. 4-1. To produce 3-, 4-, and 8-input NAND gates the manufacturer uses 3-, 4-, and
8-emitter transistors, as shown in Fig. 4-7. Because they are so basic, NAND gates are the least expensive devices in the 7400 series.
TTL load
TTL driver 74
74H
74L
74-.5_
74LS
74
74H
74L
74S
74LS
lO
12
2
12
5
8 lO 40
50
20 lOO 40
8 lO 1 lO 4
20
25
lO
50
20
10
4
NOR Gates
To get other logic functions the manufacturer modifies the basic NAND-gate design. For instance, Fig. 4-8 shows a 2input NOR gate. Q1 , Q2 , Q3 , and Q4 are the same as in the basic design. Q 5 and Q 6 have been added to produce oRing.
Notice that Q 2 and Q 6 are in parallel, the key to the oRing followed by inversion to get NORing.
Chapter 4
1TL Circuits
53
----------------------------
r-------.-------------~------~---+5V
4kQ
------
The input currents are the same as those of a standard NAND gate, but the output currents are 3 times as high, which means that the 7437 can drive heavier loads.
Appendix 3 includes several other buffer-drivers.
a
A
01
y
8 _________..r
Os
Fig. 4-8 TTL
NOR
~
,y ' y,
J~f,
-
gate.
-
..-I<J--e d (a)
I
I
(b)
Fig. 4-9 Seven-segment display.
When A and B are both low, Q 1 and Q 5 are saturated; this cuts off Q 2 and Q6 . Then Q 3 acts like an emitter follower and we get a high output.
If A orB or both are high, Q 1 or Q 5 or both are cut off, forcing Q2 or Q6 or both to tum on. When this happens,
Q4 saturates and pulls the output down to a low voltage.
With more transistors, manufacturers can produce 3- and
4-input NOR gates. (A TTL 8-input NOR gate is not available.)
AND
and
OR
Gates
To produce the AND function, another common-emitter stage is inserted before the totem-pole output of the basic
NAND gate design. The extra inversion converts the NAND gate to an AND gate. Similarly, another CE stage can be inserted before the totem-pole output of Fig. 4-8; this converts the NOR gate to an OR gate.
Buffer-Drivers
A buffer is a device that isolates two other devices.
Typically, a buffer has a high input impedance and a low output impedance. In terms of digital ICs, this means a low input current and a high output current.
Since the output current of a standard TTL gate can be
10 times the input current, a basic gate does a certain amount of buffering (isolating). But it's only when the manufacturer optimizes the design for high output currents that we call a device a buffer or driver.
As an example, the 7437 is a quad 2-input NAND buffer, meaning four 2-input NAND gates optimized to get high output currents. Each gate has the following worst-case values of input and output currents: l1L = -1.6 rnA loL = 48 rnA
54
1/H
=
loH =
Digital Computer Electronics
40 f.LA
-1.2 rnA
Encoders and Decoders
A number of TTL chips are available for encoding and decoding data. For instance, the 74147 is a decimal-toBCD encoder. It has 10 input lines (decimal) and 4 output lines (BCD). As another example, the 74154 is a 1-of-16 decoder. It has 4 input lines (binary) and 16 output lines
(hexadecimal).
Seven-segment decoders (7446, 7447, etc.) are useful for decimal displays. They convert a BCD nibble into an output that can drive a seven-segment display. Figure 4-9a illustrates the idea behind a seven-segment LED display. It has seven separate LEDs that allow you to display any digit between 0 and 9. To display a 7, the decoder will tum on
LEDs a, b, and c (Fig. 4-9b).
Seven-segment displays are not limited to decimal numbers. For instance, in some microprocessor trainers, sevensegment displays are used to indicate hexadecimal digits.
Digits A, C, E, and F are displayed in uppercase form; digit B is shown as a lowercase b (LEDs c, d, e, f, g); and digit D as a lowercase d (LEDs b, c, d, e, g).
Schmitt Triggers
When a computer is running, the outputs of gates are rapidly switching from one state to another. If you look at these signals with an oscilloscope, you see signals that ideally resemble rectangular waves like Fig. 4-10a.
When digital signals are transmitted and later received, they are often c"orrupted by noise, attenuation, or other factors and may wind up looking like the ragged waveform shown in Fig. 4-lOb. If you try to use these nonrectangular signals to drive a gate or other digital device, you get unreliable operation.
This is where the Schmitt trigger comes in. It designed to clean up ragged looking pulses, producing almost vertical
(discussed in the next section), latches and flip-flops (Chap.
7), registers and counters (Chap. 8), and memories (Chap.
9).
(a)
4-5 AND·OR•INVERT GATES
Figure 4-12a shows an AND-OR circuit. Figure 4-12b shows the De Morgan equivalent circuit, a NAND-NAND network.
In either case, the boolean equation is
(b)
_n_-
Schmitt trigger (4-1)
Y = AB +CD
Since NAND gates are the preferred TTL gates, we would build the circuit of Fig. 4-12b. NAND-NAND circuits like this are important because with them you can build any desired logic circuit (discussed in Chap. 5).
(c)
Fig. 4-10 Schmitt trigger produces rectangular output.
TTL Devices
Is there any TTL device with the output given by Eq. 4-1?
Yes, there are some AND-OR gates but they are not easily derived from the basic NAND-gate design. The gate that is easy to derive and comes close to having an expression like
Eq. 4-1 is the AND-OR-INVERT gate shown in Fig. 4-12c.
In other words, a variety of circuits like this are available on chips. Because of the inversion, the output has an equation of
(a)
(4-2)
Y = AB +CD
A
~
~
Fig. 4-11 (a) Hex Schmitt-trigger inverters; (b) 4-input
Schmitt trigger; (c) 2-input NAND Schmitt trigger.
8
NAND
c
D
(a)
transitions between the low and high state, and vice versa
(Fig. 4-IOc). In other words, the Schmitt trigger produces a rectangular output, regardless of the input waveform.
The 7414 is a hex Schmitt-trigger inverter, meaning six
Schmitt-trigger inverters in one package like Fig. 4-11a.
Notice the hysteresis symbol inside each inverter; it designates the Schmitt-trigger function.
Two other TTL Schmitt triggers are available. The 7413 is a dual4-input NAND Schmitt trigger, two Schmitt-trigger gates like Fig. 4-llb. The 74132 is a quad 2-input NAND
Schmitt trigger, four Schmitt-trigger gates like Fig. 4-11c.
A
8 y c
D
(b)
A
8
c
D
Other Devices
(c)
The 7400 series also includes a number of other devices that you will find useful, such as AND-OR-INVERT gates
Fig. 4-12 (a) AND-OR circuit; (b)
OR-INVERT circuit.
NAND-NAND
Chapter 4
circuit; (c)
TTL Circuits
AND-
55
4k0
1.6 kO
1300
I,
A
y
8
c-----....r
(a)
D ---------'
Fig. 4-13
AND-OR-INVERT
schematic diagram.
Figure 4-13 shows the schematic diagram of a TTL ANDOR-INVERT gate. Q,, Q 2 , Q 3 , and Q 4 form the basic 2-input
NAND gate of the 7400 series. By adding Q 5 and Q6 we convert the basic NAND gate to an AND-OR-INVERT gate.
Q 1 and Q5 act like 2-input AND gates; Q 2 and Q 6 produce
ORing and inversion. Because of this, the circuit is logically equivalent to Fig. 4-12c.
In Table 4-6, listing the AND-OR-INVERT gates available in the 7400 series, 2-wide means two AND gates across, 4wide means four AND gates across, and so on. For instance, the 7454 is a 2-input 4-wide AND-OR-INVERT gate like Fig.
4-14a; each AND gate has two inputs (2-input) and there are four AND gates (4-wide). Figure 4-14b shows the 7464; it is a 2-2-3-4-input 4-wide AND-OR-INVERT gate.
When we want the output given by Eq. 4-1, we can connect the output of a 2-input 2-wide AND-OR-INVERT gate to another inverter. This cancels out the internal inversion, giving us the equivalent of an AND-OR circuit (Fig. 4-12a) or a NAND-NAND network (Fig. 4-12b).
Expandable
AND-OR-INVERT
Gates
The widest AND-OR-INVERT gate available in the 7400 series is 4-wide. What do we do when we need a 6- or 8-wide circuit? One solution is to use an expandable AND-ORINVERT gate.
TABLE 4-6. AND-OR-INVERT GATES
56
Device
Description
7451
7454
7459
7464
Dual 2-input 2-wide
2-input 4-wide
Dual 2-3 input 2-wide
2-2-3-4 input 4-wide
Digital Computer Electronics
(b)
Fig. 4-14 Examples of AND-OR-INVERT circuits.
Figure 4-15a shows the schematic diagram of an expandable AND-OR-INVERT gate. The only difference between this and the preceding AND-OR-INVERT gate (Fig. 4-13) is collector and emitter tie points brought outside the package.
Since Q 2 and Q 6 are the key to the ORing operation, we are being given access to the internal ORing function. By connecting other gates to these new inputs we can expand the width of the AND-OR-INVERT gate.
Figure 4-15b shows the logic symbol for an expandable
AND-OR-INVERT gate. The arrow input represents the emitter, and the bubble stands for the collector. Table 4-7 lists the expandable AND-OR-INVERT gates in the 7400 series.
Expanders
What do we connect to the collector and emitter inputs of an expandable gate? The output of an expander like Fig.
4-16a. The input transistor acts like a 4-input AND gate.
The output transistor is a phase splitter; it produces two
TABLE 4-7. EXPANDABLE AND-OR·
INVERT GATES
Device
7450
7453
7455
Description
Dual 2-input 2-wide
2-input 4-wide
4-input 2-wide
Collector
+5
4kS1
v
1.6 kQ
A
8
y
c
A
D
y
8
c
Collector
06
Emitter
D
Emitter
(a)
(b)
Fig. 4-15 (a) Expandable AND-OR-INVERT gate;
+5
(b)
logic symbol.
v
4kS1
Collector
~Collector
~Emitter
Emitter
(b)
(a)
y
y
y
(c)
Fig. 4-16 (a) Expander; (b) symbol for expander; (c) expander driving expandable AND-OR-INVERT gate; (d) AND-OR-INVERT circuit; (e) expandable AND-OR-INVERT with two expanders.
output signals, one in phase (emitter) and the other inverted
(collector). Figure 4-16b shows the symbol of a 4-input expander. Visualize the outputs of Fig. 4-16a connected to the collector and emitter inputs of Fig. 4-15a. Then Q8 is in parallel with Q 2 and Q6 • Figure 4-16c shows the logic circuit. This means that the expander outputs are being oRed with the signals of the AND-OR-INVERT gate. In other
(d)
(e)
words, Fig. 4-l6c is equivalent to the AND-OR-INVERT circuit of Fig. 4-16d.
We can connect more expanders. Figure 4-16e shows two expanders driving the expandable gate. Now we have a 2-2-4-4-input 4-wide AND-OR-INVERT circuit.
The 7460 is a dual 4-input expander. The 7450, a dual expandable AND-OR-INVERT gate, is designed for use with up to four 7460 expanders. This means that we can add two more expanders in Fig. 4-16e to get a 2-2-4-4-4-4input 6-wide AND-OR-INVERT circuit.
Chapter 4
TTL Circuits
57
4-6 OPEN-COLLECTOR GATES
Instead of a totem-pole output, some TTL devices have an open-collector output. This means they use only the lower transistor of a totem-pole pair. Figure 4-17 a shows a 2input NAND gate with an open-collector output. Because the collector of Q 4 is open, a gate like this won't work properly until you connect an external pull-up resistor, shown in Fig. 4-17b.
Data Selection
Figure 4-18 shows a 16-to-1 multiplexer, also called a data selector. The input data bits are D 0 to D 15 • Only one of these is transmitted to the output. Control word ABCD determines which data bit is passed to the output. For instance, when
ABCD
=
0000
the upper AND gate is enabled but all other AND gates are disabled. Therefore, data bit D0 is transmitted to the output, giving y =Do
If the control word is changed to
ABCD
=
1111
the bottom gate is enabled and all other gates are disabled.
In this case,
(a)
Boolean Function Generator
+5
v
Pull-up resistor Digital design often starts with a truth table. The problem then is to come up with an equivalent logic circuit.
Multiplexers give us a simple way to transform a truth table into an equivalent logic circuit. The idea is to use input data bits that are equal to the desired output bits of the truth table.
For example, look at the truth table of Table 4-8. When the input word ABCD is 0000, the output is 0; when ABCD
TABLE 4-8
(b)
Fig. 4-17 Open-collector TTL: (a) circuit; (b) with pull-up resistor.
The outputs of open-collector gates can be wired together and connected to a common pull-up resistor. This is known as WIRE-OR. The big disadvantage of open-collector gates is their slow switching speed.
Open-collector gates are virtually obsolete because a new device called the three-state switch appeared in the early
1970s. Section 8-8 discusses three-state switches in detail.
4-7 MULTIPLEXERS
Multiplex means "many into one." A multiplexer is a circuit with many inputs but only one output. By applying control signals we can steer any input to the output.
58
Digital Computer Electronics
A
B
c
D
y
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
0
1
0
0
0
0
0
I
0
1
0
I
0
0
0
0
0
0
0
0
1
0
A
8
cc
~ ~ ~ ~
-r\
.
o,
'
L-1
'
:~"""'.
i.-1
\
J
'
L....l
'
-L--1
J
J
I
y
I
Dg
o,,
J
-r---'\
i.-1
~
i.-1
'
Fig. 4-18 A 16-to-1 multiplexer.
Chapter 4
TTL Circuits
59
-----------------····---
A
8
c
D
Universal Logic Circuit
The 74150 is a 16-to-1 multiplexer. This TTL device is a universal logic circuit because you can use it to get the hardware equivalent of any four-variable truth table. In other words, by changing the input data bits the same IC can be made to generate thousands of different truth tables.
0
0
0
0
0
1
0
0
0
0
0
0
1
0
16 to 1 data selector/
y
Multiplexing Words
Figure 4-20 illustrates a word multiplexer that has two input words and one output word. The input word on the left is
L3 L2L,L0 and the one on the right is R 3R 2R 1R0 . The control signal labeled RIGHT selects the input word that will be transmitted to the output. When RIGHT is low, the four
NAND gates on the left are activated; therefore,
Fig. 4-19 Generating a boolean function.
= 0001 , the output is 1; when ABCD = 0010, the output is 0; and so on. Figure 4-19 shows how to set up a multiplexer with the foregoing truth table. When ABCD
0000, data bit 0 is steered to the output; when ABCD
= 0001, data bit 1 is steered to the output; when ABCD
= 0010, data bit 0 is steered to the output; and so forth.
As a result, the truth table of this circuit is the same as
Table 4-8.
When RIGHT is high,
The 74157 is TTL multiplexer with an equivalent circuit like Fig. 4-20. Appendix 3 lists other multiplexers available in the 7400 series.
OUT
Fig. 4-20 Nibble multiplexer.
GLOSSARY bipolar Having two types of charge carriers: free electrons and holes. chip A small piece of semiconductor material. Sometimes, chip refers an IC device including its pins.
60
Digital Computer Electronics
fanout The maximum number of TTL loads that a TTL device can drive reliably over the specified temperature range. low-power Schottky TTL A modification of standard TTL
in which larger resistances and Schottky diodes are used.
The increased resistances decrease the power dissipation, and the Schottky diodes increase the speed. multiplexer A circuit with many inputs but only one output. Control signals select which input reaches the output. noise margin The amount of noise voltage that causes unreliable operation. With TTL it is 0.4 V. As long as noise voltages induced on connecting lines are less than
0.4 V, the TTL devices will work reliably. saturation delay time The time delay encountered when a transistor tries to come out of the saturation region. When the base drive switches from high to low, a transistor cannot instantaneously come out of saturation; extra carriers that flooded the base region must first flow out of the base.
Schmitt trigger A digital circuit that produces a rectangular output from any input large enough to drive the Schmitt trigger. The input waveform may be sinusoidal, triangular, distorted, and so on. The output is always rectangular. sink A place where something is absorbed. When saturated, the lower transistor in a totem-pole output acts like a current sink because conventional charges flow through the transistor to ground. source A place where something originates. The upper transistor of a totem-pole output acts like a source because charges flow out of its emitter into the load. standard TTL The initial TTL design with resistance values that produce a power dissipation of 10 mW per gate and a propagation delay time of 10 ns.
SELF-TESTING REVIEW
Read each of the following and provide the missing words.
Answers appear at the beginning of the next question.
7.
1.
Small-scale integration, abbreviated
, refers to fewer than 12 gates on the same chip.
Medium-scale integration (MSI) means 12 to 100 gates per chip. And large-scale integration (LSI) refers to more than gates per chip.
2. (SSI, /00) The two basic technologies for digital
ICs are bipolar and MOS. Bipolar technology is preferred for and , whereas
MOS technology is better suited to LSI. The reason
MOS dominates the LSI field is that more _ _ __ can be fabricated on the same chip area.
3. (SS/, MSI, MOSFETs) Some of the bipolar families include DTL, TTL, and ECL. has become the most widely used bipolar family. _ __ is the fastest logic family; it's used in high-speed applications. 4. (TTL, ECL) Some of the MOS families are PMOS, dominates the LSI
NMOS, and CMOS. field, and is used extensively where lowest power consumption is necessary.
5. (NMOS, CMOS) The 7400 series, also called standard TTL, contains a variety of SSI and _ _ __ chips that allow us to build all kinds of digital circuits and systems. Standard TTL has a multipleemitter input transistor and a _____ output.
The totem-pole output produces a low output impedance in either state.
6. (MSI, totem-pole) Besides standard TTL, there is high-speed TTL, low-power TTL, Schottky TTL, and low-power
TTL. Standard TTL and low-power TTL have become the favorites of digital designers, used more than any other bipolar families.
8.
9.
10.
11.
(Schottky, Schottky) 7400-series devices are guaranteed to work reliably over a range of 0 to 70°C and over a voltage range of 4.75 to 5.25 V.
A floating TTL input has the same effect as a
_ _ _ _ input.
(temperature, high) A
TTL device can sink up to 16 rnA and can source up to 400 fLA.
The maximum number of TTL loads a TTL device can drive is called the
. With standard
TTL, the fanout equals _ _ __
(standard, fanout, 10) A buffer is a device that isolates other devices. Typically, a buffer has a high input impedance and a output impedance. In terms of digital ICs, this means a _ _ __ input current and a high output current capability.
(low, low) A Schmitt trigger is a digital circuit that produces a output regardless of the input waveform. It is used to clean up ragged looking pulses that have been distorted during transmission from one place to another.
(rectangular) A multiplexer is a circuit with many inputs but only one output. It is also called a data selector because data can be steered from one of the inputs to the output. A 74150 is a 16-to-1 multiplexer. With this TTL device you can implement the logic circuit for any four-variable truth table.
Chapter 4
TTL Circuits
61
PROBLEMS
+5
v
a
~
,y ' y,
130Q
03
J~f,
o, v, ~
Va
I
I
d
(a)
04
(b)
Fig. 4-22
Fig. 4-21
4-1.
4-2.
4-3.
4-4.
62
-
-
In Fig. 4-21 a grounded input means that almost the entire supply voltage appears across the 4-kll resistor. Allowing 0.7 V for the emitter-base voltage of Q 1 , how much input emitter current is there with a grounded input? The supply voltage can be as high as 5.25 V and the 4-kll resistance can be a low as 3.28 kll. What is the input emitter current in this case?
What is the fanout of a 74SOO device when it drives low-power TTL loads?
What is the fanout of a low-power Schottky device driving standard TTL devices?
Section 4-4 gave the input and output currents for a
7437 buffer. What is the fanout of a 7437 when it drives standard TTL loads?
Digital Computer Electronics
4-5.
4-6.
4-7.
4-8.
4-9.
4-10.
A seven-segment decoder is driving a LED display like Fig. 4-22a. Which LEDs are on when digit 8 appears? Which LEDs are on when digit 4 appears?
Section 4-7 described the 74150, a 16-to-1 multiplexer. Refer to Fig. 4-23 and indicate the values the D 0 to D 15 inputs of a 74150 should have to reproduce the following truth table: The output is high when ABCD = 0000, 0100, 0111, 1100, and 1111; the output is low for all other inputs.
What is propagation delay?
Why are 5400 series devices not normally used in commercial applications?
What do Schottky devices virtually eliminate which makes their high switching speeds possible?
What is the noise margin of TTL devices?
A
8
~ ~
c
D
7 l7
1\
Do
'
_.)
01
02
03
-r---\
04
05
-!...-1
'
-L-J
\
06
-L-J
07
\
Dg
-L-J
l
I
y
j
Dg
1"'\
010
-L-1
/
011
j
012
013
014
-L-1
'
_J
015
Fig. 4-23
Chapter 4
TTL Circuits
63
BOOLEAN ALGEBRA AND
KARNAUGH MAPS
This chapter discusses boolean algebra and Karnaugh maps, topics needed by the digital designer. Digital design usually begins by specifying a desired output with a truth table.
The question then is how to come up with a logic circuit that has the same truth table. Boolean algebra and Karnaugh maps are the tools used to transform a truth table into a practical logic circuit.
;=D-y
~=D-y
(a)
;=o--y :=o---y
(b)
5-l BOOLEAN RELATIONS
What follows is a discussion of basic relations in boolean algebra. Many of these relations are the same as in ordinary algebra, which makes remembering them easy.
Given a 2-input OR gate, you can transpose the input signals without changing the output (see Fig. 5-l a). In boolean terms A+B=B+A
64
+
(B
+
C) = (A
(d)
8
A
y
c
(e)
Fig. S-1 Commutative, associative, and distributive laws.
(5-2)
BA
The foregoing relations are called commutative laws.
The next group of rules are called the associative laws.
The associative law for ORing is
A
~~y
(5-1)
Similarly, you can transpose the input signals to a 2-input
AND gate without affecting the output (Fig. 5-lb). The boolean equivalent of this is
=
(c)
~=U-=0-y
Commutative, Associative, and
Distributive Laws
AB
;~y
~D=D--y
+
B)
+
C
(5-3)
Figure 5-lc illustrates this rule. The idea is that how you group variables in an ORing operation has no effect on the output. For either gate in Fig. 5-l c the output is
Y=A+B+C
Similarly, the associative law for ANDing is
A(BC) = (AB)C
Another boolean relation is
A+A=A
(5-4)
(5-7)
which is illustrated in Fig. 5-2b. You can see what happens.
If A is 0, the output is 0; if A is 1, the output is 1; therefore, a variable ORed with itself equals the variable.
Figure 5-2c shows the next boolean rule:
Figure 5-1d illustrates this rule. How you group variables in ANDing operations has no effect on the output. For either gate of Fig. 5-1d the output is
Y =ABC
A
+
1 = 1
(5-8)
The distributive law states that
A(B
+
C) = AB
+
AC
In a nutshell, if one input to an OR gate is 1, the output is
1 regardless of the other input.
Finally, we have
(5-5)
This is easy to remember because it's identical to ordinary algebra. Figure 5-1e shows the meaning in terms of gates.
OR
A+A=
(5-9)
shown in Fig. 5-2d. In this case, a variable ORed with its complement equals 1.
Operations
The next four boolean relations are about OR operations.
Here is the first:
A+O=A
AND
The first AND relation to know about is
(5-6)
A· 1 =A
This says that a variable ORed with 0 equals the variable.
For better grasp of this idea, look at Fig. 5-2a. (The solid arrow stands for "implies.") The two cases on the left imply the case on the right. In other words, if the variable is 0, the output is 0 (left gate); if the variable is 1, the output is 1 (middle gate); therefore, a variable ORed with
0 equals the variable (right gate).
~=D-o
and
Operations
(5-10)
illustrated in Fig. 5-3a. If A is 0, the output is 0; if A is 1, the output is 1; therefore, a variable ANDed with 1 equals the variable.
Another relation is
A· A= A
~=D--1
(5-11)
=> :=D-A
(a)
~=D-o
and
:=D--1 =>
~=D-A
(b)
~=D--1
and
:=D--1 =>
~=D-1
(c)
~=D--1
and
~=D--1
=> ;=D--1
(d)
Fig. 5-2
OR
relations.
Chapter 5
Boolean Algebra and Kamaugh Maps
65
~=D-o
and
:=o---1
:=o-A
:::>
(a)
~=D-o
and
:=0---1 => :=0---A
(b)
:=D-o
and
~=D-o
:=o---0
=>
(c)
~=D-o
and
~=D-o
=> ;=Q-o
(d)
Fig. 5-3
AND
relations.
shown in Fig. 5-3b. In this case, a variable ANDed with itself equals the variable.
Figure 5-3c illustrates this relation
A· 0
=
0
(5-12)
The rule is clear. If one input to an AND gate is 0, the output is 0 regardless of the other input.
The last AND rule is
Duality Theorem
We state the duality theorem without proof. Starting with a boolean relation, you can derive another boolean relation by 1.
2.
3.
Changing each OR sign to an AND sign
Changing each AND sign to an OR sign
Complementing each 0 and I
For instance, Eq. 5-6 says that
A ·A= 0
(5-13)
A+O=A
As shown in Fig. 5-3d, a variable ANDed with its complement produces a 0 output.
The dual relation is
A· I= A
Double Inversion and De Morgan's Theorems
The double-inversion rule is
A=A
(5-14)
which says that the double complement of a variable equals the variable. Finally, there are the De Morgan theorems discussed in Chap. 3:
A+ B = AB
AB=A+B
(5-15)
(5-16)
You should memorize Eqs. 5-1 to 5-16 because they are used frequently in design work.
66
Digital Computer Electronics
This is obtained by changing the OR sign to an AND sign, and by complementing the 0 to get a 1.
The duality theorem is useful because it sometimes produces a new boolean relation. For example, Eq. 5-5 states that
A(B
By changing each relation A
+
OR
+ BC
C) = AB
+ AC
and AND operation we get the dual
= (A
+ B)(A +
C)
This is a new boolean relation, not previously discussed.
(If you want to prove it, construct the truth table for the
left and right members of the equation. The two truth tables will be identical.)
TABLE 5-l. TWO VARIABLES
A B
Fundamental product
Summary
0 0
For future reference, here are some boolean relations and their duals:
0
AB
AB
AB
AB
AB = BA
A+B=B+A
A
+
(B
A(B
+
+
C) = (A
C) =
AB
+
+
B)
+
C
AC
A+O=A
A + 1 = 1
A+A=A
A+A=1
A=A
A+ B = AB
A+AB=A
A+AB=A+B
A(BC) = (AB)C
A+ BC =
(A + B)(A + C)
A· 1 =A
A· 0 = 0
AA =A
Ali= o
A=A
AB=A+B
A(A +B) =A
A (A+ B) = AB
5-2 SUM-OF-PRODUCTS METHOD
Digital design often starts by constructing a truth table with a desired output (0 or 1) for each input condition. Once you have this truth table, you transform it into an equivalent logic circuit. This section discusses the sum-of-products method, a way of deriving a logic circuit from a truth table.
A"=D--_
A8
8
(a)
(b)
A=D---
_
8
0
A8
(c)
(d)
Fig. 5-4 Fundamental products.
Fundamental Products
Figure 5-4 shows the four possible ways to AND two input signals and their complements. In Fig. 5-4a the inputs are
A and B. Therefore, the output is
Y=AB
The output is high only when A = 0 and B = 0.
Figure 5-4b shows another possibility. Here the inputs are A and B; so the output is
In this case, the output is 1 only ~hen A = 0 and B
In Fig. 5-4c the inputs are A and B. The output
1.
Y = AB
is high only when A = 1 and B = 0. Finally, in Fig.
5-4d the inputs are A and B. The output y = AB
is 1 only when A = 1 and B = 1.
Table 5-1 summarizes the four possible ways to AND two signals in complemented or uncomplemented form. The logical productsAB, AB, Aii, andAB are called fundamental products because each produces ~_!ligh output for its corresponding input. For instance, AB is a 1 when A is 0 and B is 0, AB is a 1 when A is 0 and B is 1, and so forth.
Three Variables
A similar idea applies to three signals in complemented and uncomplemented form. Given A, B, C, and t~:~_eE"5o~£le ments, there are eight fundamental products: ABC, ABC,
ABC, ABC, ABC, ABC, ABC, and ABC. Table 5-2 lists each input possibility and its fundamental product. Again notice this property: each fundamental product is high for the corresponding input. This means that ABC is a 1 when
A is 0, B is 0, and C is 0; ABC is a 1 when A is 0, B is
0, and C is 1; and so on.
TABLE 5-2. THREE VARIABLES
A B
c
Fundamental product
0
0
0
ABC
ABC
ABC
ABC
ABC
ABC
ABC
ABC
0
0
0
0
1
0
0
Y= AB
Chapter 5
0
1
0
1
0
Boolean Algebra and Kamaugh Maps
67
Four Variables
TABLE 5-4
TABLE 5-3
When there are 4 input variables, there are 16 possible input conditions, 0000 to 1111. The corresponding fundamental products are from ABCD through ABCD. Here is a quick way to find the fundamental product for any input condition. Whenever the input variable is 0, the same variable is complemented in the fundamental product. For instance, if the input condition is 0110, the fundamental product is ABCD. Similarly, if the input is 0100, the fundamental product is ABCD.
A
B
c
y
A
B
c
D
y
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1 ~ABC
1
1
0
0
0
0
0
1
0
1 ~ABC
1 ~ABC
1 ~ABC
Deriving a Logic Circuit
To get from a truth table to an equivalent logic circuit OR the fundamental products for each input condition that produces a high output. For example, suppose you have a truth table like Table 5-3. The fundamental products are listed for each high output. By ORing these products you get the boolean equation
Y = ABC
+ ABC + ABC + ABC
ABCD
+ ABCD + ABCD
-
A
8
8
0
0
0
1
0
1
1
0
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
0
0
0
0
-
AA88CCDD
y
Fig. 5-6
(5-18)
This ~~_ation implies that three AND gates are driving an
OR gate. The first AND gat~ has inputs of A, B, C, and D; the second has inputs of A, B, C, and D; the third has
A
1
0
0
0
-
=
1
0
0
(5-17)
This e.quati_<:>n implies four AND gates driving an OR gate.
The first AND gate has in~ts of A, B, and C; the second
AND gate has inputs of A, B, and C; the third AND gate has inputs of A, B, and C; the fourth AND gate has inputs of
A, B, and C. Figure 5-5 shows the corresponding logic circuit. This AND-OR circuit has the same truth table as
Table 5-3.
As another example of the sum-of-products method, look at Table 5-4. Find each output 1 and write its fundamental p~~uct. The resulting products are ABCD, ABCD, and
AB CD. This means that the boolean e_guatiQ!! is
Y
0
1
c c
inputs of A, B, C, and D. Figure 5-6 is the equivalent logic circuit. The sum-of-products method always works. You OR the fundamental products of each high output in the truth table.
This giv\':s an equation which you can transform into ari
AND-OR network that is the circuit equivalent of the truth table. 5-3 ALGEBRAIC SIMPLIFICATION y Fig. 5-5 Sum-of-products circuit.
68
Digital Computer Electronics
After obtaining a sum-of-products equation as described in the preceding section, the thing to do is to simplify the circuit if possible. One way to do this is with boolean algebra. Here is the approach. Starting with the boolean equation for the sum-of-products circuit, you try to rearrange and simplify the equation as much as possible using the boolean rules of Sec. 5-1. The simplified boolean equation means a simpler logic circuit. This section will give you examples. A
AA88CCDD
A
8
8
y y (a)
-
A
(a)
A
A
8
8
c
C
D
i5
A
-
8
8
Is==n-Jy
tI tt
c_;
(b)
y
A
A
8
8
~t
I -+---+--1
I
(b)
- Y
Fig. S-7
(c)
Fig. S-8
Gate Leads
A preliminary guide for comparing the simplicity of one logic circuit with another is to count the number of input gate leads; the circuit with fewer input gate leads is usually easier to build. For instance, the AND-OR circuit of Fig.
5-7 a has a total of 15 input gate leads (4 on each AND gate and 3 on the OR gate). The AND-OR circuit of Fig. 5-7b, on the other hand, has a total of 9 input gate leads. The
AND-OR circuit of Fig. 5-7b is simpler than the AND-OR circuit of Fig. 5-7a because it has fewer input gate leads.
A bus is a group of wires carrying digital signals. The
8-bit bus of Fig. 5-]_a !a~mits v~iables A, B, C, D and their complements A, B, C, and D. In the typical microcomputer, the microprocessor, memory, and I/0 units exchange data by means of buses.
Factoring to Simplify
One way to reduce the number of input gate leads is to factor the boolean equation if possible. For instance, the boolean equation
Y=AB+AB
(5-19)
has the equivalent logic circuit shown in Fig. 5-8a. This circuit has six input gate leads. By factoring Eq. 5-19 we get Y = A(B
+
The equivalent logic circuit for this is shown in Fig. 5-8b; it has only four input gate leads.
Recall that a variable ORed with its complement always equals 1; therefore,
Y = A(B
+
B) = A · 1 = A
To get this output, all we need is a connecting wire from the input to the output, as shown in Fig. 5-8c. In other words, we don't need any gates at all.
Another Example
Here is another example of how factoring can simplify a boolean equation and its corresponding logic circuit. Suppose we are given
Y
=
AB
+
AC
+
BD
+
CD
(5-20)
In this equation, two variables at a time are being ANDed.
The logical products are then ORed to get the final output.
Figure 5-9a shows the corresponding logic circuit. It has
12 input gate leads.
We can factor and rearrange Eq. 5-20 as
B)
Y = A(B
Chapter 5
+
C)
+
D(B
+
C)
Boolean Algebra and Kamaugh Maps
69
A
8
C
In general, one approach in digital design is to transform a truth table into a sum-of-products equation, which you then simplify as much as possible to get a practical logic circuit. D
y
5-4 KARNAUGH MAPS
Many engineers and technicians don't simplify equations with boolean algebra. Instead, they use a method based on
Karnaugh maps. This section tells you how to construct a
Kamaugh map.
(a)
8
A
8
C
A
D
A
y
8
8
8
8
8
D D []
(a)
.4
A
A
A
(b)
8
8
(c)
8
8
(b)
Fig. 5-9
(d)
(e)
Fig. 5-10 Two-variable Kamaugh map.
or as
Y
=
(A
+
D)(B
+
C)
(5-21)
In this case, the variables are first ORed, then the logical sums are ANDed. Figure 5-9b illustrates the logic circuit.
Notice it has only six input gate leads and is simpler than the circuit of Fig. 5-9a.
Final Example
In Sec. 5-2 we derived this sum-of-products equation from a truth table:
Y = ABCD
+ ABCD + ABCD
(5-22)
Figure 5-7 a shows the sum-of-products circuit. It has 15 input gate leads. We can factor the equation as
Y
= ACD(B
+B) + ABCD
or as
Y = ACD
+ ABCD
(5-23)
Figure 5-7 b shows the equivalent logic circuit; it has only nine input gate leads.
70
Digital Computer Electronics
Two-Variable Map
Suppose you have a truth table like Table 5-5. Here's how to construct the Kamaugh map. Begin by drawing Fig.
5-1 Oa. Note the order of Q!e variables and their complements; the vertic~! column has A followed by A, and the horizontal row has B followed by B.
Next, look for output 1s in Table 5-5. The first 1 output to appear is for the input of A_= 1 and B = 0. The fundamental product for this is AB. Now, enter a 1 on the
Kamaugh mae__as shown in Fig. 5-lOb. This 1 represen~ the product AB because the 1 is in the A row and the B column. Similarly, Table 5-5 has an output 1 appearing for an input of A = 1 and B = 1. The fundamental product for this is AB. When you enter a 1 on the Kamaugh map to represent AB, you get the map of Fig. 5-lOc.
The final step in the construction of the Kamaugh map is to enter Os in the remaining spaces. Figure 5-lOd shows how the Karnaugh map looks in its final form.
Here's another example of a two-variable map. In Q!e truth t~ble of Table 5-6, the fundamental products are AB and AB. When 1s are entered on the Kamaugh map for these products and Os for the remaining spaces, the completed map looks like Fig. 5-10e.
TABLE 5-5
TABLE 5-6
CD
CD
CD
CD
CD
B
y
A
B
y
AB
AB
0 0
0 .1
0
0
0
0
0
0
0
AB
AB
AB
AB
0
1
AB
AB
A
0
c
c
c
AB
AB
AB
AB
AB
AB
AB
AB
AB
AB
AB
AB
CD
CD
CD
0
0
c
0
0
AB
0
0
AB
0
0
AB
0
0
0
AB
0
0
0
0
(c)
(b)
(a)
CD
c
0
CD
CD
(b)
(a}
c
CD
0
(c)
Fig. 5-11 Three-variable Karnaugh map.
Fig. 5-12 Four-variable Karnaugh map.
Three-Variable Map
Four-Variable Map
Suppose you have a truth table like Table 5-7. Begin by drawing Fig. 5-lla. It is especially important to notice the order of the variab~~ a~d their compleEJ-ents. The vertical column is labeled A B, AB, AB, and AB. This order is not a binary progression; instead it follows the order of 00, 01,
11, and 10. The reason for this is explained in the derivation of the Karnaugh method; briefly, it's done so that only one variable changes from complemented to uncomplemented form (or vice versa).
Next, look for output 1s in Tabl~ 5J.. Th~fundamental products for these 1 outputs are ABC, ABC, and ABC.
Enter these Is on the Karnaugh map (Fig. 5-11b). The final step is to enter Os in the remaining spaces (Fig. 5-llc).
This Karnaugh map is useful because it shows the fundamental products needed for the sum-of-products circuit.
Many MSI circuits process binary words of 4 bits each
(nibbles). For this reason, logic circuits are often designed to handle four variables (or their complements). This is why the four-variable map is the most important.
Here's an example of constructing a four-variable map.
Suppose you have the truth table of Table 5-8. The first step is to draw the blank map of Fig. 5-12a. Again, notice the progression. The vertical column is labeled AB, AB,
TABLE 5-8
A
TABLE 5-7
A
0
0
0
0
B
0
0
c
0
1
0
1
0
0
0
1
0
y
B
C
D
Y
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
I
1
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
1
0
1
0
1
0
1
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
Chapter 5
[
__ _
Boolean Algebra and Karnaugh Maps
71
AB, and AB. The horizontal row is labeled CD, CD, CD, and CD.
In Table 5-8 the output 1s have these fundamental products:ABCD, ABCD, ABCD, andABCD. After entering
Is on the Kamaugh map, you will have Fig. 5-12b. The final step of filling in Os results in the completed map of
Fig. 5-12c.
goes from uncomplemented to complemented form (D to
B, and C remain uncomplemented). Whenever this happens, you can eliminate the variable that changes form.
D). The other variables don't change form (A,
Algebraic Proof
The sum-of-products equation corresponding to Fig. 5-13a
IS
5-5 PAIRS, QUADS, AND OCTETS
Y = ABCD
There is a way of using the Karnaugh map to get simplified logic circuits. But before you can understand how this is done, you will have to learn the meaning of pairs, quads, and octets.
+ ABCD
which factors into
Y = ABC(D +D)
Since D is ORed with D, the equation reduces to
CD
CD
CD
CD
0
0
0
0
AB
0
0
0
0
AB
0
0
AB
0
0
AB
CD
CD
CD
CD
Y =ABC
AB
0
0
0
0
AB
0
0
0
0
AB
0
0
AB
0
0
A pair of adjacent 1s is like those of Fig 5-l3a always means that the sum-of-products equation will have a variable and a complement that drop out.
For easy identification, it is customary t encircle a pair of adjacent Is, as shown in Fig. 5-13b. hen when you look at the map, you can tell at a glance t at one variable and its complement will drop out of the bo lean equation.
In other words, an encircled pair of ls lik those of Fig.
5-l3b no longer stands ~r the ORing o two separate products, ABCD and ABCD. The encircled pair should be visualized instead as representing a single r duced product
ABC.
Here's another example. Figure 5-13c s ows a pair of
1s that are v~ically ~ja~ent. These 1s co espond to the product ABCD and ABCD. Notice that on y one variable ch~nges from uncomplemented to comple ented form (B to B); a~other variables retain their original f rm. Therefore,
B and B drop out. This ~eans that the e circled pair of
Fig. 5-13c represents ACD.
From now on, whenever you see a pair of adjacent ls, eliminate the variable that goes from co plemented to uncomplymented form. A glance at Fig. -13d indicates
~at B changes form; therefore, the pair f 1s represents
ACD. Likewise, D_0anges form in Fig. 5- 3e; so the pair of ls stands for ABC.
If more than one pair exists on a Kam ugh map, you can OR the simplified products to get the bo lean equa~o_E_.
For instance, the lower p~ of Fig. 5-13fr presents ACD.
The upper pair stands for ABD. The corresp nding boolean equation for this map is
-
0
0
CD
CD
CD
CD
AB
0
0
0
0
AB
AB
0
0
0
0
AB
0
0
0
0
0
CD
CD
CD
0
0
0
AB
0
0
0
AB
0
0
0
0
0
0
0
0
-
-
AB
0
(d)
CD
CD
CD
CD
AB
0
0
0
0
0
AB
occ=Do
0
0
AB
0
0
0
0
0
AB
0
0
0
CD
CD
CD
CD
AB
0
0
0
0
AB
0
0
0
AB
0
0
cc=D
0
CD
(c)
AB
0
(b)
(a)
AB
cr::::::D
(e)
(f)
Fig. 5-13 Pairs on a Karnaugh map.
Y = ACD
Pairs
The map of Fig. 5-13a contains a pair of Is that are horizontally adjacent. The first 1 represents th~ product
ABCD; the second I stands for the product ABCD. As we move from the first 1 to the second 1, only one variable
72
Digital Computer Electronics
+ ABD
The Quad
A quad is a group of four 1s that are end t end, as shown in Fig. 5-14a, or in the form of a square, a shown in Fig.
co
CD
CD
CD
AB
0
0
0
0
AB
0
0
0
0
5-l4b. When you see a quad, always encircle it because it
leads to a simpler product. In fact, a quad means that two variables and their complements drop out of the boolean equation. Here's why a quad eliminates two variables. Visualize the four ls of Fig. 5-~a as two pairs (Fig. 5-14c). The first pair represents ABC; the second pair stands for ABC.
The boolean equation for these two pairs is
AB
AB
0
CD
CD
CD
CD
AB
0
0
0
0
AB
0
0
0
0
AB
AB
1
1
1
(b)
(a)
Y =ABC+ ABC
DO
Fig. 5-15 Octets on a Karnaugh map.
This factors into
Y = AB(C
+
C)
The Octet
which reduces to
An octet is a group of eight adjacent Is like those of Fig.
5-I5a. An octet always eliminates three variables and their
y = AB
complements. Here's why. Visualize the octet as two quads
(Fig. 5-15b). The equation for these two quads is
So the quad of Fig. 5-l4a represents a product where two variables and their complements drop out.
A similar proof applies to all quads. There's no need to go through the algebra again. Merely determine which variables go from complemented to uncomplemented form; these are the variables that drop out.
For instance, look at the quad of Fig. 5-14b. Pick any I as a starting point. When you move horizontally, D is the variable that changes form. When you move vertically, B changes form. Therefore, the simplified equation is
Y = AC
AB
-
AB
AB
-
AB
CD
CD
CD
CD
0
0
0
0
0
0
0
0
~
0
0
0
0
CD
CD
CD
CD
AB
0
0
0
0
AB
0
0
0
0
AB
0
0
A$
0
0
(b)
(a)
0
1
Y
=
Y
= A(C
AC
+
AC
Factoring gives
+
C)
But this reduces to
Y=A
So the octet of Fig. 5-15a means that three variables and their complements drop out of the corresponding product.
A similar proof applies to any octet. From now on, don't bother with the algebra. Just step through the 1s of the octet and determine which three variables change form.
These are the variables that drop out.
5-6 KARNAUGH SIMPLIFICATIONS
You have seen how a pair eliminates one variable, a quad eliminates two variables, and an octet eliminates three variables. Because of this, you should encircle the octets first, the quads second, and the pairs last. In this way, the greatest simplification takes place.
CD
CD
CD
CD
AB
0
0
0
0
An Example
AB
0
0
0
0
Suppose you've translated a truth table into the Kamaugh map shown in Fig. 5-l6a. Look for octets first. There are none. Next, look for quads. There are two. Finally, look for pairs. There is one. If you do it correctly, you arrive at Fig. 5-16b.
The pair represents the simplified product ABD, the lower quad stands for AC, and the quad on the right
AB
-
AB
cc:=Dcc:::D
0
0
0
(c)
Fig. 5-14 Quads on a Karnaugh map.
0
Chapter 5
Boolean Algebra and Karnaugh Maps
73
CD
AB
0
AB
0
CD
CD
CD
CD
AB
0
0
AB
0
AB
0
AB
AB
0
AB
0
CD
CD
CD
CCD~
0
0
1
0
0
represents CD. By ORing these simplified products, you get the boolean equation for the map
ABD
=
+ AC + CD
(5-26)
Y =BCD+ BCD
0
Fig. 5-16
Y
Another thing to know about is rolling. In Fig. 5-17c, the pairs result in the equation
0
(b)
(a)
Rolling the Map
(5-24)
Visualize picking up the Kamaugh map and rolling it so that the left side touches the right side. If you're visualizing correctly, you will realize the two pairs actually form a quad. To indicate this, draw half circles around each pair, as shown in Fig. 5-17d. From this viewpoint, the quad of
Fig. 5-17d has the equation
Y
=
(5-27)
BD
Why is rolling valid? Because Eq. 5-26 can be simplified to Eq. 5-27. Here's the proof. Start with Eq. 5-26:
Overlapping Groups
When you encircle groups, you are allowed to use the same
1 more than once. Figure 5-17a illustrates the idea. The simplified equation for the overlapping groups is
Y =BCD+ BCD
This factors into
Y
BD(C
=
+
C)
(5-25)
Y =A+ BCD
which reduces to
It is valid to encircle the Is as shown in Fig. 5-17b, but then the isolated 1 results in a more complicated equation:
Y =A+ ABCD
This requires a more complicated logic circuit than Eq.
5-25. So always overlap groups if possible; that is, use the
1s more than once to get the largest groups you can.
CD
AB
CD
0
0
CD
0
CD
0
CD
CD
CD
0
0
0
0
AB
AB
0
CD
0
0
AB
AB
-
AB
c
(a)
AB
AB
CD
CD
CD
CD
0
0
0
0
0
0
0
0
-
AB
0
0
a
0
CD
CD
CD
CD
AB
0
0
0
0
0
AB
0
0
0
0
AB
0
0
AB
0
CD
CD
CD
CD
AB
0
0
0
0
AB
0
AB
0
AB
0
%
1
(a)
a a 0
0
0
(b)
Fig. 5-18 Redundant group.
a
0
CD
CD
CD
CD
AB
0
0
0
0
AB
0
AB
)
0
0
0
(
AB
0
0
0
0
(c)
Fig. 5-17 Overlapping and rolling.
74
BD
(b)
-
AB
1
=
This final equation represents a rolled quad like Fig. 5-17 d.
Therefore, 1s on the edges of a Kamaugh map can be grouped with Is on opposite edges.
CD
AB
AB
Y
Digital Computer Electronics
(d)
Redundant Groups
After you finish encircling groups, there is one more thing to do before writing the simplified boolean equation: eliminate any group whose 1s are completely overlapped by other groups. (A group whose 1s are all overlapped by other groups is called a redundant group.)
Here is an example. Suppose you have encircled the three pairs shown in Fig. 5-18a. The boolean equation then is Y = BCD + ABD + ACD
At this point, you should check to see if there are any redundant groups. Notice that the 1s in the inner pair are completely overlapped by the outside pairs. Because of this, the inner pair is a redundant pair and can be eliminated to get the simpler map of Fig. 5-18b. The equation for this map is
Y =BCD
+ ACD
Since this is a simpler equation, it means a simpler logic circuit. This is why you should eliminate redundant groups if they exist.
SOLUTION
There are no octets, but there is a quad, as shown in Fig.
5-19b. By overlapping we can find two more quads (Fig.
5-19c). Finally, overlapping gives us the pair of Fig.
5-19d.
The horizontal quad of Fig. 5-19d corresponds to a simplified product of AB. The square quad on the right corresponds to AC, while the one on the left stands for AD.
The pair represents BCD. By ORing these products we get the simplified equation
Y
Summary
2.
3.
4.
5.
6.
AB
+ AC + AD + BCD
A
8
C
D
Enter a 1 on the Karnaugh map for each fundamental product that corresponds to 1 output in the truth table.
Enter Os elsewhere.
Encircle the octets, quads, and pairs. Remember to roll and overlap to get the largest groups possible.
If any isolated 1s remain, encircle them.
Eliminate redundant groups if they exist.
Write the boolean equation by ORing the products corresponding to the encircled groups.
Draw the equivalent logic circuit.
EXAMPLE
(5-28)
Figure 5-20 shows the equivalent logic circuit.
Here's a summary of how to use the Karnaugh map to simplify logic circuits:
1.
=
5-l
y
Fig. 5-20
What is the simplified boolean equation for the Karnaugh map of Fig. 5-l9a?
EXAMPLE
CD
CD
CD
CD
AB
0
0
0
0
AB
AB
0
0
0
AB
AB
AB
CD
CD
CD
0
0
0
0
0
0
-
AB
0
CD
AB
0
~
0
1
1
5-2
As you know from Chap. 4, the NAND gate is the least expensive gate in the 7400 series. Because of this, ANDOR circuits are usually built as equivalent NAND-NAND circuits. Convert the AND-OR circuit of Fig. 5-20 to a NAND-NAND circuit using 7400-series devices.
1
SOLUTION
(b)
(a)
AB
AB
AB
AB
CD
CD
CD
CD
0
0
0
0
0
0
0
:=m
1
(c)
Fig. 5-19
AB
-
AB
AB
AB
CD
CD
CD
CD
0
0
0
0
0
0
(0
0
~1
~
Th
1
1
0
(d)
-j
Replace each AND gate of Fig. 5-20 by a NAND gate and replace the final OR gate by a NAND gate. Figure 5-21 is the De Morgan equivalent of Fig. 5-20. As shown, we can build the circuit with a 7400, a 7410, and a 7420.
5-7 DON'T-CARE CONDITIONS
Sometimes, it doesn't matter what the output is for a given input word. To indicate this, we use an X in the truth table instead of a 0 or a 1. For instance, look at Table 5-9. The
Chapter 5
Boolean Algebra and Kamaugh Maps
75
A
8
C
D
CD
~--------,
I
I
74oo
._,_-r-+---r-1,
3
I
A8
CD
CD
CD
CD
CD
A8
0
0
CD
CD
0
k>-'~f----,
~
A8
y
L _______ J
2
A8
0
A8
X
A8
X
X
X
X
A8
X
X
X
X
X
(b)
(a)
I
7420
A
12
.-~----~
0
.4
8
8 c
c
D
D
b-----~
13
7410
Fig. 5-21
NAND-NAND
circuit using TTL gates. y output is an X for any input word from 1000 through 1111.
The X's are called don't cares because they can be treated either as Os or 1s, whichever leads to a simpler circuit.
Figure 5-22a shows the Kamaugh map for Table 5-9.
X's are used for ABCD, ABCD, AiiciS, ABCD, ABCD,
ABCD, ABCD, and ABCD because these are don't cares in the truth table. Figure 5-22b shows the most efficient way to encircle the groups. Notice two crucial ideas. First, we visualize all X's as Is and try to form the largest groups that include the real 1s. This gives us three quads. Second, we visualize all remaining X's as Os. In this way, the X's are used to the best advantage. We are free to do this because the don't cares can be either Os or 1s, whichever we prefer.
A
B
c
D
y
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
1
0
0
0
0
0
1
0
1
0
1
0
1
0
0
0
1
0
1
X
X
X
X
X
X
X
X
76
Figure 5-22b implies the simplified boolean equation
Y
Digital Computer Electronics
=
BD +CD+ CD
Figure 5-22c is the simplified logic circuit. This network has nine input gate leads.
EXAMPLE
TABLE 5-9
0
0
(c)
Fig. 5-22 Don't cares.
AND-OR
5-3
Recall that BCD numbers express each decimal digit as a nibble: 0 to 9 are encoded as 0000 to 1001. Especially important, nibbles 1010 to 1111 are never used in a BCD system. Table 5-10 shows a truth table for use in a BCD system.
As you see, don't cares appear for 1010 through 1111.
Construct the Kamaugh map and show the simplified logic circuit. SOLUTION
Figure 5-23a illustrates the Kamaugh map. The largest group we can form is the pair shown in Fig. 5-23b. The boolean equation is
Y =BCD
Figure 5-23c is the simplified logic circuit.
TABLE 5-10
A
B
c
D
y
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
X
X
X
X
X
X
0
0
0
0
t
0
0
0
0
0
1
0
0
\~
0
1
0
1
0
1
0
0
1'
0
CD
CD
CD
CD
AB
0
0
0
0
0
AB
0
0
X
X
AB
X
X
X
X
AB
0
0
CD
CD
CD
CD
AB
0
0
0
0
AB
0
0
AB
X
X
AB
0
0
X
X
X
(b)
(a)
'/
A .4
Q
0
8
8 c
c
D jj y (c)
Fig. 5-23 Don't cares in a BCD system.
)
GLOSSARY bus A group of wires carrying digital signals. don't care An output that may be either low or high without affecting the operation of the system. fundamental product The logical product of variables and complements that produces a high output for a given input condition. Karnaugh map A graphical display of the fundamental products in a truth table. octet A group of eight adjacent Is on a Kamaugh map.
pair A group of two adjacent Is on a Karnaugh map.
These 1s may be horizontally or vertically aligned. quad A group of four adjacent 1s on a Karnaugh map. redundant group A group of Is on a Karnaugh map all of which are overlapped by other groups. sum-of-products circuit An AND-OR circuit obtained by
ORing the fundamental products that produce output Is in a truth table.
SELF-TESTING REVIEW
Read each of the following and provide the missing words.
Answers appear at the beginning of the next question.
5.
1.
2.
3.
4.
Digital design often starts by constructing a _ __ table. By ORing the products, you get a sum-of-products equation.
(truth, fundamental) A preliminary guide for comparing the simplicity of logic circuits is to count the number of input leads. (gate) A bus is a group of carrying digital signals. In the typical microcomputer, the microprocessor, memory, and 1/0 units communicate via buses.
(wires) One way to simplify the sum-of-products
6.
7.
equation is to use boolean algebra. Another way is the map.
(Karnaugh) A pair eliminates one variable, a
_ _ _ _ eliminates two variables, and an octet eliminates variables. Because of this, you should encircle the first, the quads next, and the pairs last.
(quad, three, octets) NAND-NAND circuits are equivalent to AND-OR circuits. This is important because
_ _ _ _ gates are the least expensive gates in the
7400 series.
(NAND) When a truth table has don't cares, we enter
X's on the Kamaugh map. These can be treated as Os or Is, whichever leads to a simpler logic circuit.
Chapter 5
Boolean Algebra and Kamaugh Maps
77
PROBLEMS
5-1.
5-2.
5-3.
What are the fundamental products for each of the inputs words ABCD = 0010, ABCD = 1101,
ABCD = 1110?
A truth table has output 1s for each of these inputs: a. ABCD = 0011
b. ABCD = 0101
c. ABCD = 1000
d. ABCD = 1101
What are the fundamental products?
Draw the logic circuit for this boolean equation:
Y = ABCD + ABCD + ABCD + ABCD
5-4.
5-5.
Output 1s appear in the truth table for these input conditions: ABCD = 0001, ABCD = 0110, and
ABCD = 1110. What is the sum-of-products equation? Draw the AND-OR circuit for
5-8.
5-9.
5-10.
5-11.
5-12.
5-13.
5-14.
5-15.
5-16.
5-17.
5-18.
5-19.
5-20.
5.21.
Y = ABCD + ABCD + ABCD
5-6.
5-7.
How many input gate leads does this circuit have?
A truth table has output Is for these inputs:
ABCD = 0011, ABCD = 0110, ABCD =
1001, and ABCD = 1110. Draw the Kamaugh map showing the fundamental products.
A truth table has four input variables. The first eight outputs are Os, and the last eight outputs are
Is. Draw the Kamaugh map.
TABLE 5-11
B
c
D
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
I
1
0
0
0
0
0
I
I
0
0
0
1
0
y3 y2 yi Yo
I
0
0
1
0
I
l
0
0
0
1
0
0
0
I
0
0
0
I
0
0
0
I
0
0
0
0
0
I
1
0
0
0
1
1
0
0
I
Digital Computer Electronics
0
0
1
0
I
I
0
0
0
0
0
I
0
0
78
5.23
TABLE 5-12
A
1
0
5.22
Draw the Kamaugh map for the Y3 output of
Table 5-11. Simplify as much as possible; then draw the logic circuit.
Use the Karnaugh map to work out the simplified logic circuit for the Y2 output of Table 5-11.
Repeat Prob. 5-9 for the Y1 output.
Repeat Prob. 5-9 for the Y0 output.
Use the Karnaugh map to work out the simplified logic circuit for the Y 3 output of Table 5-12.
Repeat Prob. 5-12 for the Y2 output.
Repeat Prob. 5-12 for the Y1 output.
Repeat Prob. 5-12 for Y0 output.
A+ 0 =?
A· 1 = ?
A + 1 = ?
A· 0 =?
Use the duality theorem to derive another boolean relation from:
A+ AB =A+ B
Use the commutative law to complete the following equations.
a. A+ B =
b. AB =
Use the associative law to complete the following equations. a. A+ (B + C) =
b. A(BC) =
Use the distributive law to complete the equation
A(B + C) =
1
0
0
A
B
c
D
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 lJ 0
1
0
0
0
0
0
1
0
I
I
0
0
0
0
1
0
0
0
0
y3 y2 yi Yo
0
0
0
1
0
1
0
0
X
X
X
X
X
X
1
0
0
0
1
1
0
0
X
X
X
X
X
X
0
0
1
0
I
0
1
0
0
X
X
X
X
X
X
0
0
I
0
X
X
X
X
X
X
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