Computer Organization and Systems: Problems about Cache Memory

Topics: CPU cache, Memory address, Cache Pages: 8 (1443 words) Published: October 8, 2013
COMP212 Computer Organization and Systems

Tutorial/Lab #4

Problems about Cache Memory

4.2A two-way set associative cache has lines of 16 bytes and a total size of 8 bytes. The 64-Mbyte main memory is byte-addressable. Show the format of main memory address. Kb => 1,024
Mb => 1024 * 1024
Ans.

A two-way set => 2 lines / set in the cache;

The cache has lines of 16 bytes and a total size of 8K bytes => There are a total of 8K bytes/16 bytes = 512 lines (23*210/24) in the cache;

‘2 lines / set in the cache’ AND ‘There are a total of 512 lines in the cache’ => The cache consists of 512 lines/2 lines/set = 256 sets
=> 8 bits (256=28) are needed to identify the set number.

64-Mbyte main memory is byte-addressable
=> There are 64M units to be addressed
=> A 26-bit (26*220) address is needed;

‘The cache has lines of 16 bytes’ AND ‘64-Mbyte main memory’ => Main memory consists of 64-Mbyte/16 bytes = 222 blocks
=> The length of Tag + Set = 22
=> The length of Tag = 22-8 = 14;

The word field length is 26 – 22 = 4 bits

(Another way to calculate word field length:
The cache has lines of 16 bytes => The main memory block size is 16 bytes; The main memory is byte-addressable => The word length (size) is 1 byte; => There are 16/1=16 words in one block;
=> 4 bits (16=24) are needed to identify the word number.)

Therefore, the format of main memory is
Tag Set Word 14
8
4

4.3For the hexadecimal main memory address 111111, 666666, BBBBBB, show the following information, in hexadecimal format:
a)Tag, Line, and Word values for a direct-mapped cache, using the format of Figure 4.8 (slide 27).

Ans.

Address
(in hexadecimal format)
111111
666666
BBBBBB
Address
(in binary format)
0001 0001 0001 0001 0001 0001
0110 0110 0110 0110 0110 0110
1011 1011 1011 1011 1011 1011
Tag
0001 0001 (11h)
0110 0110 (66h)
1011 1011 (BBh)
Line
0001 0001 0001 00 (444h)
0110 0110 0110 01 (1999 h)
1011 1011 1011 10 (2EEEh)
Word
01 (1h)
10 (2h)
11 (3h)

4.4List the following values:
a)For the direct cache example of Fig.4.8: address length, number of addressable units, block size, number of blocks in main memory, number of lines in cache, size of tag.

Ans.
Address length: 24 bits
Number of addressable unit: 224, i.e. 16M unit
Block size: 22, i.e. 4 words
Number of blocks in main memory: 224/22, i.e. 222
Number of lines in cache: 214, i.e. 16K lines
Size of tag: 8 bits
b) For the associative cache example of Fig.4.10: address length, number of addressable units, block size, number of blocks in main memory, number of lines in cache, size of tag.

Ans.
Address length: 24 bits
Number of addressable unit: 224, i.e. 16M unit
Block size: 22, i.e. 4 words
Number of blocks in main memory: 224/22, i.e. 222
Number of lines in cache: 214, i.e. 16K lines
Size of tag: 22 bits

c) For the associative cache example of Fig.4.12: address length, number of addressable units, block size, number of blocks in main memory, number of lines in set, number of set, number of lines in cache, size of tag.

Ans.
Address length: 24 bits
Number of addressable unit: 224, i.e. 16M unit
Block size: 22, i.e. 4 words
Number of blocks in main memory: 224/22, i.e. 222
Number of lines in set: 2
Number of set: 213
Number of lines in cache: 214, i.e. 16K lines
Size of tag: 9 bits

4.5Consider a 32-bit microprocessor that has an on-chip 16-KByte four-way set-associative cache. Assume that the cache has a line size of four 32-bit words. Draw a block diagram of this cache showing its organization and how the different address fields are used to determine a cache hit/miss. Where in the cache is the word from memory location ABCDE8F8 mapped?

Ans.

A four-way set => 4 lines/set in the cache;

‘16-KByte cache’ AND ‘the cache has a line size of four 32-bit words’ => There are 16K*8/4*32 = 214*23/22*25...
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