CA Assignment 2

CA Assignment 2

1. a) All arrays are read simultaneously. A cache read is a hit.

LRU:

Cache power usage= (4*5) + 20 +1 = 41 units.

FIFO:
Cache power usage= (4*5) + 20 = 40 units.

Random Replacement Policy: Replacement array is not accessed.

Cache power usage= (4*5) + 20= 40units.

b) Cache Read Miss

LRU: Cache power usage= (4*5) + 4 = 24units

FIFO: Cache power usage= (4*5) + 1= 21units

Random: Cache power usage= (4*5) = 20 units

c)

LRU:
Cache power usage= (4*5) + 26 = 46 units.
FIFO:
Cache power usage= (4*5) + 25 = 45 units.

Random Replacement Policy:

Cache power usage=(4*5) + 25 = 45units.

B11.

B12. Virtual Page accessed
TLB (hit or miss)
Page table (hit or fault)
1
miss fault 5 hit X
9
miss fault 14 miss fault
10
miss hit 6 miss hit
15
miss hit 12 miss hit
7
miss hit 2 miss fault

C1.

a) Data dependencies:
1. Data dependency for register R1 from LD to DASSI.
2. Data dependency for Register R1 from DADDI to SD.
3. Data dependency for Register R2 from DADDI to DSUB.
4. Data dependency for Register R4 from DSUB to BNEZ.

b)

Clock Cycle number

Instruction
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
LD
IF
ID
EX
MEM
WB

DADDI IF
S
S
ID
EX
MEM
WB

SD

IF
S
S
ID
EX
MEM
WB

DADDI

IF
ID
EX
MEM
WB

DSUB

IF
S
S
ID
EX
MEM
WB

BNEZ