memory system
CHAPTER 5
•
THE MEMORY SYSTEM
PROBLEMS - Cap. 9 - Sistema di memoria
5.1
Give a block diagram similar to the one in Figure 5.10 for a 8M × 32 memory using
512K × 8 memory chips.
5.2
Consider the dynamic memory cell of Figure 5.6. Assume that C = 50 femtofarads
(10−15 F) and that leakage current through the transistor is about 9 picoamperes
(10−12 A). The voltage across the capacitor when it is fully charged is equal to 4.5 V.
The cell must be refreshed before this voltage drops below 3 V. Estimate the minimum refresh rate.
5.3
In the bottom right corner of Figure 5.8 there are data input and data output registers.
Draw a circuit that can implement one bit of each of these registers, and show the
Introduzione all'architettura dei calcolatori 2/ed - Carl Hamacher, Zvonko Vranesic, Safwat Zaky
Copyright © 2006 - The McGraw-Hill Companies srl
PROBLEMS
361
required connections to the block “Read/Write circuits & latches” on one side and the data bus on the other side.
5.4
Consider a main memory constructed with SDRAM chips that have timing requirements depicted in Figure 5.9, except that the burst length is 8. Assume that 32 bits of data are transferred in parallel. If a 133-MHz clock is used, how much time does it take to transfer: (a) 32 bytes of data
(b) 64 bytes of data
What is the latency in each case?
5.5
Criticize the following statement: “Using a faster processor chip results in a corresponding increase in performance of a computer even if the main memory speed remains the same.” 5.6
A program consists of two nested loops — a small inner loop and a much larger outer loop. The general structure of the program is given in Figure P5.1. The decimal memory addresses shown delineate the location of the two loops and the beginning and end of the total program. All memory locations in the various sections, 17–22, 23–164, 165–239, and so on, contain instructions to be executed in straight-line
•
THE MEMORY SYSTEM
PROBLEMS - Cap. 9 - Sistema di memoria
5.1
Give a block diagram similar to the one in Figure 5.10 for a 8M × 32 memory using
512K × 8 memory chips.
5.2
Consider the dynamic memory cell of Figure 5.6. Assume that C = 50 femtofarads
(10−15 F) and that leakage current through the transistor is about 9 picoamperes
(10−12 A). The voltage across the capacitor when it is fully charged is equal to 4.5 V.
The cell must be refreshed before this voltage drops below 3 V. Estimate the minimum refresh rate.
5.3
In the bottom right corner of Figure 5.8 there are data input and data output registers.
Draw a circuit that can implement one bit of each of these registers, and show the
Introduzione all'architettura dei calcolatori 2/ed - Carl Hamacher, Zvonko Vranesic, Safwat Zaky
Copyright © 2006 - The McGraw-Hill Companies srl
PROBLEMS
361
required connections to the block “Read/Write circuits & latches” on one side and the data bus on the other side.
5.4
Consider a main memory constructed with SDRAM chips that have timing requirements depicted in Figure 5.9, except that the burst length is 8. Assume that 32 bits of data are transferred in parallel. If a 133-MHz clock is used, how much time does it take to transfer: (a) 32 bytes of data
(b) 64 bytes of data
What is the latency in each case?
5.5
Criticize the following statement: “Using a faster processor chip results in a corresponding increase in performance of a computer even if the main memory speed remains the same.” 5.6
A program consists of two nested loops — a small inner loop and a much larger outer loop. The general structure of the program is given in Figure P5.1. The decimal memory addresses shown delineate the location of the two loops and the beginning and end of the total program. All memory locations in the various sections, 17–22, 23–164, 165–239, and so on, contain instructions to be executed in straight-line