X Masking Techniques and Test Data Compaction of Logic Bist

Topics: Automatic test pattern generation, Electronic design automation, Digital electronics Pages: 65 (19343 words) Published: July 30, 2013
B.E. PROJECT ON X-MASKING TECHNIQUES AND TEST DATA COMPACTION FOR LOGIC BUILT-IN SELF TEST A DISSERTATION SUBMITTED TOWARDS THE PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE AWARD OF A DEGREE IN BACHELOR OF ENGINEERING IN ELECTRONICS AND COMMUNICATION Submitted By HIMANSHU DOVAL VARUN KAPOOR (2K7/EC/643) (2K7/EC/713)

UNDER THE GUIDANCE OF
DR. ASOK BHATTACHARYYA

DEPARTMENT OF ELECTRONICS AND COMMUNICATION DELHI COLLEGE OF ENGINEERING 2011

ABSTRACT

Testing is done for checking the integrated circuits for manufacturing faults introduced during semiconductor processing. Testing typically consists of applying a set of test stimuli to the inputs of the circuit under test (CUT) while analyzing the output responses. An Automated test Equipment (ATE) is used to generate the test stimuli and analyze the output.

Logic built-in self-test (LBIST) is a design for testability (DFT) technique in which a portion of a circuit on a chip, board, or system is used to test the digital logic circuit itself. A typical logic BIST system contains a test pattern generator (TPG) which automatically generates test patterns for application to the inputs of the circuit under test; an output response analyzer (ORA) which automatically compacts the output responses of the CUT into a signature. This signature is compared with a golden signature to decide whether the chip contains manufacturing faults. The most significant advantage of LBIST is that it does not require the expensive ATE and it makes on-field testing possible.

To make Logic BIST solution practically applicable there are a few problems which one has to deal with. These are associated with the hardware as well as with the software. Hardware (Multiple Input Shift Register) needs to be protected from the flow of don’t cares and software issues deal with the Test data Compaction which is necessary so as to reduce the on chip tester memory. ii

CERTIFICATION

This is to certify that the project entitled “LOGIC BUILT-IN SELF TEST”, submitted by HIMANSHU DOVAL (2K7/EC/643) and VARUN KAPOOR (2K7/EC/713) for the partial fulfillment of the award of Bachelor of Engineering in Electronics and Communication, is a bonafide record of the candidates under my guidance. To the best of my knowledge, this work has not been submitted for the award of any other degree.

Dr. Asok Bhattacharyya Professor, Electronics and Communication Engineering Delhi College of Engineering

DATE: PLACE: iii

ACKNOWLEDGMENT

This B.E thesis has been carried out under the able guidance of

Dr. Asok

Bhattacharyya, and under the aegis of Department of Electronics and Communication, Delhi College of Engineering. We would like to express our profound gratitude and appreciation to our advisor, Dr. Asok Bhattacharyya, for his constant guidance, support, and encouragement throughout the project course. He models many of the high quality characteristics that we aspire to emulate during our professional and personal life. Working with him has been a source of honor and pride for us. The authors consider it a pleasant duty to record their profound sense of gratitude and indebtedness to Mr. Swapnil Bahl, Specialist, STMicroelectronics for his invaluable support and guidance, his supervision and untiring interest during each and every phase of this Project. He has been an invaluable source of motivation and encouragement throughout the course of project. We extend our thanks to STMicroelectronics for mobilizing the resources and providing support at our hand without which the project would not have sailed successfully. We would also like to thank all the faculty members and staff of the Department of ECE for their co-operation and readiness to always help us when needed.

HIMANSHU DOVAL VARUN KAPOOR

(2K7/EC/643) (2K7/EC/713)

iv

TABLE OF CONTENTS
Page No.

CERTIFICATE ACKNOWLEDGEMENT TABLE OF CONTENTS ABSTRACT

1

INTRODUCTION 1.1 Importance of Testing 1.2 Yield and Reject Rate 1.3...
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