The Sentaurus TCAD Simulation
Figure. 1 illustrates the device architecture of the simulated tapered FinFET and cross-section of the device. The 5nm node technology was used in this simulation. This is equal to effective gate length approximately equal to 10 nm [10]. In this simulation, the physical gate length (LG) of 9 nm are adopted. SiO2 and Si3N4 are considered as the gate oxide and spacer material, respectively. Fixed spacer length (LSP) of 7 nm was used. The doping concentrations are the source (1020 cm-3), the drain (1020 cm-3), and the channel (1016 cm-3). The dimension of different parameters for the simulated device is tabulated in Table 1.
The Sentaurus TCAD simulator was used to perform 3-D simulations, which included the density gradient (DG) solver model …show more content…
Figure. 4 depicts electron distributions across the fin in the channel region of NFET and PFET in the on-state (VD=0.5V and VG=0.5V), respectively. Under this condition, the highest electron density (NFET) and the hole density (PFET) are generally located in the middle and near the top of the fin. Because the tapered fin structure has FWT shorter than FWB, the electron distribution by side gates of the tapered fin is not perpendicular to the box. For different FH of NFET (Figure. 4(a)), we can see that highest electron concentration exist at the top of the fin. This maximum electron density is forced into the fin volume due to quantum confinement in the very narrow fin (such as the triangular). The on-state current will follow the fin perimeter FinFET shapes. The wider FWT has ten times higher on-current than for the smaller one in the same FH. This is due to the combination of several factors, from the larger perimeter length, larger channel area, and better gate control of wider FWT.
Similar analysis for the PFET, the hole will concentrate follow the fin perimeters, and happens mainly at the top of the fin in the higher FH rather than at mid-fin. Compare to NFET in the FH = 48nm and FWT = 5nm, the holes show a preferential movement towards the mid-fin whereas electrons prefer to reside near the surface sidewalls. This is maybe caused by the mobility of holes much slower in the PFET than the electrons in the
The Sentaurus TCAD simulator was used to perform 3-D simulations, which included the density gradient (DG) solver model …show more content…
Figure. 4 depicts electron distributions across the fin in the channel region of NFET and PFET in the on-state (VD=0.5V and VG=0.5V), respectively. Under this condition, the highest electron density (NFET) and the hole density (PFET) are generally located in the middle and near the top of the fin. Because the tapered fin structure has FWT shorter than FWB, the electron distribution by side gates of the tapered fin is not perpendicular to the box. For different FH of NFET (Figure. 4(a)), we can see that highest electron concentration exist at the top of the fin. This maximum electron density is forced into the fin volume due to quantum confinement in the very narrow fin (such as the triangular). The on-state current will follow the fin perimeter FinFET shapes. The wider FWT has ten times higher on-current than for the smaller one in the same FH. This is due to the combination of several factors, from the larger perimeter length, larger channel area, and better gate control of wider FWT.
Similar analysis for the PFET, the hole will concentrate follow the fin perimeters, and happens mainly at the top of the fin in the higher FH rather than at mid-fin. Compare to NFET in the FH = 48nm and FWT = 5nm, the holes show a preferential movement towards the mid-fin whereas electrons prefer to reside near the surface sidewalls. This is maybe caused by the mobility of holes much slower in the PFET than the electrons in the