The Ripple Adder: Programming an FPGA Using VHDL
School: Architecture, Computing & Engineering
BENG HONS Electrical and Electronic
Embedded Systems and IC Design
Assessment Deadline: 08/May/2013
Component Number: 001
To be completed by student:
I confirm that no part of this assignment, except where clearly quoted and referenced, has been copied from material belonging to any other person e.g. from a book, handout, another student. I am aware that it is a breach of UEL regulations to copy the work of another without clear acknowledgement and that attempting to do so renders me liable to proceedings under the
Academic Misconduct Regulations.
UNIVERSITY OF EAST LONDON
EE3003 – EMBEDDED SYSTEMS AND IC DESIGN
The Ripple Adder
Programming an FPGA using VHDL
Author Student ID:
Students are introduced to using VHDL to program FPGA’s, rather than using Schematic Capture software. They build 4 and 8 bit ripple adders and learn exactly where the term “ripple” comes from.
Furthermore they are introduced programming and simulating their VHDL code in the software called
Assignment to complete:
1. Identify the bit patterns for the 4-bit adder which are being added in the test bench code and the sum and carry expected.
Figure 1.1 – Output waveform of 4-bit adder VHDL code
As seen in above figure (fig.1.1) the simulated output shows the bit patterns to be added and the result, including the carry out. The code to produce above waveform, can be found in Appendix 2.
Within the test bench code, the input/stimulus part of the code (see appendix 2, table b, lines 63 - 72) shows the above described bits, being applied.
The sum result is correct as seen below:
Carry Bit (4)