Nor Gate

3) NOR GATE

Schematic View:

Program:

* SPICE export from S-Edit 12.00 Tue Sep 15 04:22:22 2009
* Design: NOR
* Cell: Cell0
* View: view0
* Export as: Top level Cell
* Netlist port order: default
* Exclude model statements: no
* Expand paths: yes
* Root path: E:\__________________________

********* Simulation Settings - General section *********
.probe
.option probev

********* Simulation Settings - Parameters and SPICE Options *********

.include "C:\Documents and Settings\user\My Documents\Tanner EDA\T-Spice v12.0\models\ml2_20.md"
.tran 1ns 1000ns
.print v(Ina) v(Inb) v(Out) v1 Ina Gnd pulse(.1 5 .1ns .1ns .1ns 50ns 100ns) v2 Inb Gnd pulse (.1 5 .1ns .1ns .1ns 100ns 200ns) v3 Vdd Gnd 5.0

MMOSFET_N_1 Out Ina Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
MMOSFET_N_2 Gnd Inb Out Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
MMOSFET_P_1 N_1 Ina Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
MMOSFET_P_2 N_1 Inb Out Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u ********* Simulation Settings - Analysis section *********

.end

Simulation Output:

T-Spice - Tanner SPICE
Version 12.00
Network license from: 169.254.58.239
Product Release ID: T-Spice Win32 12.00.20060502.03:07:23
Copyright (c) 1993-2006 Tanner Research, Inc.

Opening output file "C:\DOCUME~1\user\LOCALS~1\Temp\Cell0.out"
Parsing "C:\DOCUME~1\user\LOCALS~1\Temp\Cell0.sp"
Initializing parser from header file "C:\lodfem\ml1_typ.md"
Including "C:\Documents and Settings\user\My Documents\Tanner EDA\T-Spice v12.0\models\ml2_20.md"

Probing options: probev = 1

Device and node counts: MOSFETs - 4 MOSFET geometries - 2 BJTs - 0 JFETs - 0 MESFETs - 0 Diodes - 0
Capacitors - 0 Resistors - 0 Inductors - 0 Mutual inductors - 0
Transmission