memory chip

L7: Memory Basics and Timing

Acknowledgements:
Materials in this lecture are courtesy of the following sources and are used with permission.
Nathan Ickes
Rex Min
Yun Wu

J. Rabaey, A. Chandrakasan, B. Nikolic. Digital Integrated Circuits: A Design Perspective.
Prentice Hall/Pearson, 2003.
L7: 6.111 Spring 2006

Introductory Digital Systems Laboratory

1

Memory Classification & Metrics

Read-Write Memory

Random
Access

Non-Random
Access

SRAM

FIFO

DRAM

Non-Volatile
Read-Write
Memory

Read-Only
Memory (ROM)

LIFO

EPROM

Mask-Programmed

E2PROM
FLASH

Key Design Metrics:
1. Memory Density (number of bits/μm2) and Size
2. Access Time (time to read or write) and Throughput
3. Power Dissipation
L7: 6.111 Spring 2006

Introductory Digital Systems Laboratory

2

Memory Array Architecture

2L-K

AL-1

Storage Cell

Row Decode

AK
AK+1

Bit Line

Word Line

2L-K row by Mx2K column cell array

K

M.2

Amplify swing to rail-to-rail amplitude

Sense Amps/Driver
A0
AK-1

Column Decode

Selects appropriate word
(i.e., multiplexor)

Input-Output
(M bits)

L7: 6.111 Spring 2006

Introductory Digital Systems Laboratory

3

Latch and Register Based Memory
Positive Latch Negative Latch

Register Memory
Negative latch Positive latch

D
0
D

1
Q

1

CLK

D Q

D

Q
0

G

QM

D Q

Q

G

Clk

CLK

Works fine for small memory blocks (e.g., small register files)
Inefficient in area for large memories – density is the key metric in large memory circuits

How do we minimize cell size?
L7: 6.111 Spring 2006

Introductory Digital Systems Laboratory

4

Static RAM (SRAM) Cell (The 6-T Cell)
BL

BL
WL

WL

M2
M5

Q
M1

BL

WL

Q

VDD

Q

M4
Q

M6

M3
BL

Write: set BL and BL to 0 and VDD or VDD and 0 and then enable WL (i.e., set to VDD)
Read: Charge BL and BL to VDD and then enable WL (i.e., set to