Implementation of Risc Processor in Fpga Using Verilog

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1. INTRODUCTION

Reduced instruction-set computers (RISC) are designed to have a small set of instructions that execute in short clock cycles, with a small number of cycles per instruction. RISC machines are optimized to achieve efficient pipelining of their instruction streams. The machine also serves as a starting point for developing architectural variants and a more robust instruction set

Designers make high-level tradeoffs in selecting an architecture that serves an application. Once architecture has been selected, a circuit that has sufficient performance (speed) must be synthesized. Hardware description languages (HDLs) play a key role in this process by modeling the system and serving as a descriptive medium that can be used by a synthesis tool.

2. RISC (Reduced Instruction Set Computer)

The nature of RISC architecture and semiconductors rapid technical improvements, RISC embedded platforms have become the best choice for embedded applications.

RISC performance characteristics:

Power Critical

Battery powered and typically less than 2 Watts of power consumption for a whole SBC using an ARM processor, compared to around 15+ Watts for a x86-based SBC.

Space Critical

With a low power solution, the main system can fit into very compact space, eliminating heat dissipation concerns.

Environmental Critical

Because of the lack of heat generation, the RISC system can be fully enclosed for total protection from the environment

Cost Critical

RISC embedded solutions usually come with application-oriented processors that provide a lower cost of ownership because of faster time to market, less development risk and greater overall added value.

Typical RISC applications:

• Industrial mobile platforms

• Touch based Human Machine Interface (HMI)

• Point of information (POI) or Point of Scales (POS)

• In vehicle – Telemetric

• Data collector

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