Impact of Media on Business
PHANI KUMAR YEKULA Mobile: 91 9527005959 E-mail: phani5465@gmail.com
Objective:
To become a successful professional in the field of food and beverages and to work in an innovative and competitive world which will help me to explore myself fully and realize my potential willing to work as a key player in challenging & creative environment. So, I can contribute to the growth and success of the organization.
1 Scholastic Background:
❖ B.Tech (E.C.E) from Gudlavalleru Engineering College, affiliated to the JNTU, Kakinada (2005-2009) with 63%. ❖ Board of Intermediate Education from Sai Vikas Residential College (2001-2003) with 61%. ❖ SSC, Board of Secondary Education from Amaleswari Residential High School, (2000-2001) with 58%.
2 Technical Profile:
Programming Languages : Fundamentals in ‘C’ and JSE. Operating Systems : WINDOWS 2000, WINDOWS XP. Areas Interest : Telecommunications, Networking. SAP 710 : Material Management
Project Experience:
Soft wares : Active VHDL 6.3,XILINX 7.1
Language : VHDL
Duration : 3 months Team Size : 4
Project Description:
The project FPGA Implementation of Low Power Parallel Multiplier to reduce power losses and decrease the thermal losses. Multiplier is commonly used in DSP and communication applications. In FPGA design power reduction is possibly only through reduced switching activity, Which is also call Dynamic Power. In general dynamic power consumption is defined as the power consumed while the clock is running and external inputs are switching. This project presents a multiplier design in which switching activities are reduced through architecture optimization.
Role: Involved in coding and debugging of user
Objective:
To become a successful professional in the field of food and beverages and to work in an innovative and competitive world which will help me to explore myself fully and realize my potential willing to work as a key player in challenging & creative environment. So, I can contribute to the growth and success of the organization.
1 Scholastic Background:
❖ B.Tech (E.C.E) from Gudlavalleru Engineering College, affiliated to the JNTU, Kakinada (2005-2009) with 63%. ❖ Board of Intermediate Education from Sai Vikas Residential College (2001-2003) with 61%. ❖ SSC, Board of Secondary Education from Amaleswari Residential High School, (2000-2001) with 58%.
2 Technical Profile:
Programming Languages : Fundamentals in ‘C’ and JSE. Operating Systems : WINDOWS 2000, WINDOWS XP. Areas Interest : Telecommunications, Networking. SAP 710 : Material Management
Project Experience:
Soft wares : Active VHDL 6.3,XILINX 7.1
Language : VHDL
Duration : 3 months Team Size : 4
Project Description:
The project FPGA Implementation of Low Power Parallel Multiplier to reduce power losses and decrease the thermal losses. Multiplier is commonly used in DSP and communication applications. In FPGA design power reduction is possibly only through reduced switching activity, Which is also call Dynamic Power. In general dynamic power consumption is defined as the power consumed while the clock is running and external inputs are switching. This project presents a multiplier design in which switching activities are reduced through architecture optimization.
Role: Involved in coding and debugging of user