International Journal of Theoretical and Applied Computer Sciences Volume 1 Number 1 (2006) pp. 9–34 (c) GBS Publishers and Distributors (India) http://www.gbspublisher.com/ijtacs.htm
Implementation and Evaluation of Image Processing Algorithms on Reconfigurable Architecture using C-based Hardware Descriptive Languages Daggu Venkateshwar Rao*, Shruti Patil, Naveen Anne Babu and V Muthukumar Department of Electrical and Computer Engineering University of Nevada Las Vegas. Las Vegas, NV 89154 *E-mail: firstname.lastname@example.org Abstract With the advent of mobile embedded multimedia devices that are required to perform a range of multimedia tasks, especially image processing tasks, the need to design efficient and high performance image processing systems in a short time-to-market schedule needs to be addressed. Image Processing algorithms implemented in hardware have emerged as the most viable solution for improving the performance of image processing systems. The introduction of reconfigurable devices and system level hardware programming languages has further accelerated the design of image processing in hardware. Most of the system level hardware programming languages introduced and commonly used in the industry are highly hardware specific and requires intermediate to advance hardware knowledge to design and implement the system. In order to overcome this bottleneck various C-based hardware descriptive languages have been proposed over the past decade . These languages have greatly simplified the task of designing and verifying hardware implementation of the system. However, the synthesis process of the system to hardware was not completely addressed and was conducted using manual methods resulting in duplication of the implementation process. Handel-C is a new C-based language proposed that provides direct implementation of hardware from the C-based language description of the system. Handel-C language and the IDE tool introduced by Celoxica Ltd. provides both simulation and synthesis capabilities. This work evaluates the performance and efficiency of Handel-C language on image processing algorithms and is compared at simulation level with another popular C-based system level language called SystemC and at synthesis level with the industry standard Hardware Descriptive language,
Daggu Venkateshwar Rao et al Verilog. The image processing algorithms considered include, image filtering, image smoothing and edge detection. Comparison parameters at simulation level include, man-hours for implementation, compile time and lines of code. Comparison parameters at synthesis level include logic resources required, maximum frequency of operation and execution time. Our evaluations show that the Handel-C implementation perform better at system and synthesis level compared to other languages considered in this work. The work also proposes a novel hardware architecture to implement Canny’s edge detection algorithm. The proposed architecture is capable of producing one edge-pixel every clock cycle. A comparison of our architecture for Canny’s edge detection with other architecture is also discussed.
Digital image processing is an ever expanding and dynamic area with applications reaching out into our everyday life such as medicine, space exploration, surveillance, authentication, automated industry inspection and many more areas. Applications such as these involve different processes like image enhancement and object detection . Implementing such applications on a general purpose computer can be easier, but not very time efficient due to additional constraints on memory and other peripheral devices. Application specific hardware implementation offers much greater speed than a software implementation. With advances in the VLSI (Very Large Scale Integrated) technology hardware implementation has become an attractive alternative. Implementing complex computation tasks on hardware and by exploiting...
Please join StudyMode to read the full document